initial commit

.gitignore

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+/Makefrag.pkgs
+target
+*.jar
+*.stamp

.gitmodules

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+[submodule "rocket-chip"]
+	path = rocket-chip
+	url = git@github.com:ucb-bar/rocket-chip.git
+[submodule "testchipip"]
+	path = testchipip
+	url = git@github.com:ucb-bar/testchipip.git

Makefrag

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+lib_dir=$(base_dir)/lib
+
+ROCKETCHIP_DIR=$(base_dir)/rocket-chip
+EXTRA_PACKAGES=testchipip
+
+rocketchip_stamp=$(base_dir)/lib/rocketchip.stamp
+SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar
+extra_stamps = $(addprefix $(lib_dir)/,$(addsuffix .stamp,$(EXTRA_PACKAGES)))
+
+lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null)
+
+libs: $(rocketchip_stamp) $(extra_stamps)
+
+$(rocketchip_stamp): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR))
+	cd $(ROCKETCHIP_DIR) && $(SBT) pack
+	mkdir -p $(lib_dir)
+	cp $(ROCKETCHIP_DIR)/target/pack/lib/*.jar $(lib_dir)
+	touch $(rocketchip_stamp)
+
+-include $(base_dir)/Makefrag.pkgs
+
+$(base_dir)/Makefrag.pkgs: $(base_dir)/generate-pkg-mk.sh
+	bash $(base_dir)/generate-pkg-mk.sh $(EXTRA_PACKAGES) > $@
+
+FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar
+FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
+
+$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala)
+	$(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala
+
+build_dir=$(sim_dir)/generated-src
+
+CHISEL_ARGS ?=
+
+$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir: $(rocketchip_stamp) $(extra_stamps) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)
+	mkdir -p $(build_dir)
+	cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
+
+$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v: $(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir $(FIRRTL_JAR)
+	$(FIRRTL) -i $< -o $@ -X verilog

bootrom/.gitignore

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+*.elf
+*.dump

bootrom/Makefile

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+bootrom_img = bootrom.img
+
+GCC=riscv64-unknown-elf-gcc
+OBJCOPY=riscv64-unknown-elf-objcopy
+OBJDUMP=riscv64-unknown-elf-objdump
+
+all: $(bootrom_img)
+
+%.img: %.elf
+	$(OBJCOPY) -O binary --change-addresses=-0x1000 --only-section .text $< $@
+
+%.elf: %.S linker.ld
+	$(GCC) -Tlinker.ld $< -nostdlib -static -o $@
+
+%.dump: %.elf
+	$(OBJDUMP) -d $< > $@

bootrom/bootrom.S

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+.text
+.global _start
+_start:
+  // This boot ROM doesn't know about any boot devices, so it just spins,
+  // waiting for the serial interface to load the program and interrupt it
+  j setup_wfi_loop // reset vector
+  .word 0 // reserved
+  .word 0 // reserved
+  .word 0 // pointer to config string
+default_trap_vec:
+  j boot_trap // default trap vector
+  .word 0
+  .word 0
+  .word 0
+
+setup_wfi_loop:
+  la a0, default_trap_vec
+  csrw mtvec, a0
+  li a0, 8 // MIE or MSIP bit
+  csrw mie, a0 // set only MSIP in mie CSR
+  csrw mideleg, zero // no delegation
+  csrs mstatus, a0 // set MIE in mstatus CSR
+wfi_loop:
+  wfi
+  j wfi_loop
+
+boot_trap:
+  csrr a0, mhartid
+  sll a0, a0, 2 // offset for hart msip
+  li a1, 0x2000000 // base address of clint
+  add a0, a0, a1
+  sw zero, 0(a0) // clear the interrupt
+  li a0, 0x80000000 // program reset vector
+  csrw mepc, a0 // return from interrupt to start of user program
+  mret

bootrom/linker.ld

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+SECTIONS
+{
+    . = 0x1000;
+    .text : { *(.text) }
+}

build.sbt

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+organization := "edu.berkeley.cs"
+
+version := "1.0"
+
+name := "testchip-example"
+
+scalaVersion := "2.11.7"

generate-pkg-mk.sh

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+#!/bin/sh
+
+base_dir=$(dirname $0)
+
+for pkg in $@
+do
+    pkg_dir="${base_dir}/${pkg}"
+    cat <<MAKE
+${base_dir}/lib/${pkg}.stamp: \$(call lookup_scala_srcs, ${pkg_dir}) \$(rocketchip_stamp)
+	rm -f ${pkg_dir}/lib
+	ln -s ${base_dir}/lib ${pkg_dir}/lib
+	cd ${pkg_dir} && \$(SBT) package
+	cp ${pkg_dir}/target/scala-2.11/*.jar ${base_dir}/lib
+	touch \$@
+MAKE
+done

src/main/scala/Configs.scala

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+package example
+
+import cde.{Parameters, Config, CDEMatchError}
+import testchipip.WithSerialAdapter
+import chisel3._
+import diplomacy.LazyModule
+
+class WithExampleTop extends Config(
+  (pname, site, here) => pname match {
+    case BuildExampleTop => (p: Parameters) => LazyModule(new ExampleTop(p))
+    case _ => throw new CDEMatchError
+  })
+
+class SerialAdapterConfig extends Config(
+  new WithSerialAdapter ++ new rocketchip.BaseConfig)
+
+class DefaultExampleConfig extends Config(
+  new WithExampleTop ++ new SerialAdapterConfig)

src/main/scala/TestHarness.scala

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+package example
+
+import util.GeneratorApp
+import diplomacy.LazyModule
+import rocketchip._
+import testchipip._
+import chisel3._
+import cde.{Parameters, Field}
+
+case object BuildExampleTop extends Field[Parameters => ExampleTop]
+
+class TestHarness(implicit val p: Parameters) extends Module {
+  val io = new Bundle {
+    val success = Bool(OUTPUT)
+  }
+
+  def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop(p))
+
+  val dut = p(BuildExampleTop)(p).module
+  val ser = Module(new SimSerialWrapper(p(SerialInterfaceWidth)))
+
+  val nMemChannels = dut.io.mem_axi.size
+  for (axi <- dut.io.mem_axi) {
+    val mem = Module(new SimAXIMem(BigInt(p(ExtMemSize) / nMemChannels)))
+    mem.io.axi <> axi
+  }
+
+  ser.io.serial <> dut.io.serial
+  io.success := ser.io.exit
+}
+
+object Generator extends GeneratorApp {
+  val longName = names.topModuleProject + "." +
+                 names.topModuleClass + "." +
+                 names.configs
+  generateFirrtl
+}

src/main/scala/Top.scala

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+package example
+
+import chisel3._
+import cde.Parameters
+import diplomacy.LazyModule
+import testchipip._
+import rocketchip._
+
+class ExampleTop(q: Parameters) extends BaseTop(q)
+    with PeripheryBootROM with PeripheryCoreplexLocalInterrupter
+    with PeripherySerial with PeripheryMasterMem {
+  override lazy val module = Module(
+    new ExampleTopModule(p, this, new ExampleTopBundle(p)))
+}
+
+class ExampleTopBundle(p: Parameters) extends BaseTopBundle(p)
+  with PeripheryBootROMBundle with PeripheryCoreplexLocalInterrupterBundle
+  with PeripheryMasterMemBundle with PeripherySerialBundle
+
+class ExampleTopModule(p: Parameters, l: ExampleTop, b: => ExampleTopBundle)
+  extends BaseTopModule(p, l, b)
+  with PeripheryBootROMModule with PeripheryCoreplexLocalInterrupterModule
+  with PeripheryMasterMemModule with PeripherySerialModule
+  with HardwiredResetVector with DirectConnection with NoDebug

vsim/.gitignore

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+/DVEfiles
+/csrc
+/simv-*
+/output
+/generated-src
+/ucli.key
+/vc_hdrs.h

vsim/Makefile

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+base_dir=$(abspath ..)
+sim_dir=$(abspath .)
+
+PROJECT ?= example
+MODEL ?= TestHarness
+CONFIG ?= DefaultExampleConfig
+CFG_PROJECT ?= $(PROJECT)
+TB ?= TestDriver
+
+simv = simv-$(PROJECT)-$(CONFIG)
+simv_debug = simv-$(PROJECT)-$(CONFIG)-debug
+
+default: $(simv)
+
+debug: $(simv_debug)
+
+include $(base_dir)/Makefrag
+
+sim_vsrcs = \
+	$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v \
+	$(base_dir)/testchipip/vsrc/TestDriver.v \
+	$(base_dir)/testchipip/vsrc/SimSerial.v
+
+sim_csrcs = \
+	$(base_dir)/testchipip/csrc/SimSerial.cc
+
+VCS = vcs -full64
+
+VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
+	+rad +v2k +vcs+lic+wait \
+	+vc+list -CC "-I$(VCS_HOME)/include" \
+	-CC "-I$(RISCV)/include" \
+	-CC "-std=c++11" \
+	-CC "-Wl,-rpath,$(RISCV)/lib" \
+	$(RISCV)/lib/libfesvr.so \
+	-sverilog \
+	+incdir+$(generated_dir) \
+	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
+	+define+PRINTF_COND=$(TB).printf_cond \
+	+define+STOP_COND=!$(TB).reset \
+	+define+RANDOMIZE_MEM_INIT \
+	+define+RANDOMIZE_REG_INIT \
+	+define+RANDOMIZE_GARBAGE_ASSIGN \
+	+define+RANDOMIZE_INVALID_ASSIGN \
+	+libext+.v \
+
+verilog: $(sim_vsrcs)
+
+$(simv): $(sim_vsrcs) $(sim_csrcs)
+	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+	-debug_pp
+
+$(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
+	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+	+define+DEBUG -debug_pp