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bump rocket-chip to enable large memory spaces (#76)

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* bump rocket-chip to enable large memory spaces

* Tests pass with write mask bug fix

* fix verisim build

* Update to point to rocket-chip on master

* bump rocket-chip and barstools

This fixes the analog chisel bug and
incorporates the firrtl MDF support (h/t John Wright)
This commit is contained in:
Colin Schmidt
2019-05-14 10:22:31 -07:00
committed by GitHub
parent 00d8e04d93
commit e007b49179
7 changed files with 116 additions and 9 deletions
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16
Makefrag
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@@ -8,7 +8,7 @@ SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch
lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null)
PACKAGES=rocket-chip testchipip
PACKAGES=rocket-chip testchipip barstools
SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)
ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*"
@@ -25,7 +25,11 @@ build_dir=$(sim_dir)/generated-src
CHISEL_ARGS ?=
ifneq ($(PROJECT),example)
long_name=$(PROJECT).$(CONFIG)
else
long_name=$(PROJECT).$(MODEL).$(CONFIG)
endif
FIRRTL_FILE ?=$(build_dir)/$(long_name).fir
ANNO_FILE ?=$(build_dir)/$(long_name).anno.json
@@ -35,6 +39,9 @@ TOP_ANNO ?=$(build_dir)/$(long_name).top.anno.json
HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v
HARNESS_FIR ?=$(build_dir)/$(long_name).harness.fir
HARNESS_ANNO ?=$(build_dir)/$(long_name).harness.anno.json
HARNESS_SMEMS_FILE ?=$(build_dir)/$(long_name).harness.mems.v
HARNESS_SMEMS_CONF ?=$(build_dir)/$(long_name).harness.mems.conf
HARNESS_SMEMS_FIR ?=$(build_dir)/$(long_name).harness.mems.fir
SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v
SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf
SMEMS_FIR ?=$(build_dir)/$(long_name).mems.fir
@@ -43,6 +50,7 @@ sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF)
$(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR)
cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
@@ -56,7 +64,7 @@ $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FI
cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)"
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)"
grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
@@ -64,6 +72,10 @@ MACROCOMPILER_MODE ?= --mode synflops
$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF)
cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)"
HARNESS_MACROCOMPILER_MODE = --mode synflops
$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF)
cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)"
regression-tests = \
rv64ud-v-fcvt \
rv64ud-p-fdiv \