wu-arch/chipyard
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Fix some build system problems.

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1) Bump testchipip to include forgotten commit
2) Add some support for generating VCS files
3) Fix some makefile deps
This commit is contained in:
Paul Rigge
2019-03-06 22:10:31 -08:00
parent c7d56c09a0
commit 8a522ba404
5 changed files with 46 additions and 26 deletions
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8
Makefrag
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@@ -33,7 +33,7 @@ VERILOG_FILE ?=$(build_dir)/$(long_name).top.v
HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v
SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v
SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf
verilator_dotf ?= $(build_dir)/verilator_files.f
sim_dotf ?= $(build_dir)/sim_files.f
REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
@@ -54,10 +54,10 @@ $(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/barstools/macros/src
.PHONY: jars
jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
$(verilator_dotf): $(SCALA_SOURCES)
cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir)"
$(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR)
cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(verilator_dotf)
$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
mkdir -p $(build_dir)
cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"