e007b49179
* bump rocket-chip to enable large memory spaces * Tests pass with write mask bug fix * fix verisim build * Update to point to rocket-chip on master * bump rocket-chip and barstools This fixes the analog chisel bug and incorporates the firrtl MDF support (h/t John Wright)
112 lines
5.0 KiB
Plaintext
112 lines
5.0 KiB
Plaintext
ROCKETCHIP_DIR=$(base_dir)/rocket-chip
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TESTCHIP_DIR = $(base_dir)/testchipip
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SCALA_VERSION=2.12.4
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SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
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SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION)
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lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null)
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PACKAGES=rocket-chip testchipip barstools
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SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)
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ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*"
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TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes"
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FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
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$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala)
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$(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala
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mkdir -p $(dir $@)
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cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@
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touch $@
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build_dir=$(sim_dir)/generated-src
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CHISEL_ARGS ?=
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ifneq ($(PROJECT),example)
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long_name=$(PROJECT).$(CONFIG)
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else
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long_name=$(PROJECT).$(MODEL).$(CONFIG)
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endif
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FIRRTL_FILE ?=$(build_dir)/$(long_name).fir
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ANNO_FILE ?=$(build_dir)/$(long_name).anno.json
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VERILOG_FILE ?=$(build_dir)/$(long_name).top.v
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TOP_FIR ?=$(build_dir)/$(long_name).top.fir
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TOP_ANNO ?=$(build_dir)/$(long_name).top.anno.json
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HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v
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HARNESS_FIR ?=$(build_dir)/$(long_name).harness.fir
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HARNESS_ANNO ?=$(build_dir)/$(long_name).harness.anno.json
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HARNESS_SMEMS_FILE ?=$(build_dir)/$(long_name).harness.mems.v
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HARNESS_SMEMS_CONF ?=$(build_dir)/$(long_name).harness.mems.conf
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HARNESS_SMEMS_FIR ?=$(build_dir)/$(long_name).harness.mems.fir
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SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v
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SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf
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SMEMS_FIR ?=$(build_dir)/$(long_name).mems.fir
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sim_dotf ?= $(build_dir)/sim_files.f
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sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
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sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
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REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
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HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF)
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$(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR)
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cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
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$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
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mkdir -p $(build_dir)
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cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
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$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
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cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
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cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
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$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
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cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)"
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grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
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# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
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MACROCOMPILER_MODE ?= --mode synflops
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$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF)
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cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)"
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HARNESS_MACROCOMPILER_MODE = --mode synflops
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$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF)
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cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)"
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regression-tests = \
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rv64ud-v-fcvt \
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rv64ud-p-fdiv \
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rv64ud-v-fadd \
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rv64uf-v-fadd \
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rv64um-v-mul \
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rv64mi-p-breakpoint \
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rv64uc-v-rvc \
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rv64ud-v-structural \
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rv64si-p-wfi \
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rv64um-v-divw \
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rv64ua-v-lrsc \
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rv64ui-v-fence_i \
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rv64ud-v-fcvt_w \
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rv64uf-v-fmin \
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rv64ui-v-sb \
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rv64ua-v-amomax_d \
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rv64ud-v-move \
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rv64ud-v-fclass \
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rv64ua-v-amoand_d \
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rv64ua-v-amoxor_d \
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rv64si-p-sbreak \
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rv64ud-v-fmadd \
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rv64uf-v-ldst \
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rv64um-v-mulh \
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rv64si-p-dirty
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output_dir=$(sim_dir)/output
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$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/%
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mkdir -p $(output_dir)
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ln -sf $< $@
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