Commit Graph

390 Commits

Author SHA1 Message Date
Zitao Fang
a02700a1d4 Add documentation for sodor 2020-09-18 23:14:47 -07:00
Zitao Fang
0c8771c35e Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate 2020-09-18 22:33:42 -07:00
Zitao Fang
a43400acb9 Update CI 2020-09-18 15:36:33 -07:00
Jerry Zhao
b9622c5132 Merge remote-tracking branch 'origin/dev' into serial-tl 2020-09-18 01:00:13 -07:00
Jerry Zhao
269af01a70 Bump testchipip 2020-09-16 13:51:33 -07:00
Jerry Zhao
36ccb12560 Bump testchipip 2020-09-16 10:29:03 -07:00
Zitao Fang
1543acfacd Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate 2020-09-14 23:55:05 -07:00
Zitao Fang
642441e0a2 Replaced memory and fixed 3-stage single port arbiter 2020-09-14 23:54:52 -07:00
Jerry Zhao
0d8e87126c Deprecate support for on-chip SerialAdapter 2020-09-14 19:43:32 -07:00
Jerry Zhao
f9cc1dc2c2 Merge remote-tracking branch 'origin/dev' into serial-tl 2020-09-14 19:35:43 -07:00
Jerry Zhao
10625a3a6c Undo regression in iocells flexibility 2020-09-14 13:27:31 -07:00
Jerry Zhao
16c80112a7 Merge pull request #670 from ucb-bar/harness-refactor
Split IOBinders into IOBinders and HarnessBinders | punch out clocks to harness for simwidgets and bridges
2020-09-14 12:45:46 -07:00
Zitao Fang
5506f77679 Add CircleCI check and update Sodor config 2020-09-14 09:14:57 -07:00
Jerry Zhao
6c5bce5430 Support Tilelink over serial 2020-09-13 11:59:16 -07:00
Jerry Zhao
d2b42cee2c Bump testchipip 2020-09-12 23:31:54 -07:00
Jerry Zhao
a5385c0a54 Update testchipip/icenet to use rocket-chip Located API 2020-09-11 00:02:07 -07:00
Zitao Fang
15d53e2cda Bump to the latest Rocket 2020-09-09 15:12:37 -07:00
Jerry Zhao
facef464e6 Update BridgeBinders | fix runtime HarnessBinder port type checks 2020-09-09 00:15:02 -07:00
Jerry Zhao
8f9574fd79 Clean up passing ports from IOBinders to HarnessBinders 2020-09-08 22:30:17 -07:00
Jerry Zhao
11a9ad2428 Address code review comments 2020-09-08 15:52:09 -07:00
Jerry Zhao
7ed02a7d38 Fix Typos 2020-09-07 11:36:37 -07:00
Zitao Fang
fb7804070c Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate 2020-09-06 23:09:50 -07:00
Zitao Fang
11dcd71a48 Clean up 5-stage instruction fetch 2020-09-06 23:06:00 -07:00
Jerry Zhao
927244bf2e DTM only supports HTIF in DMI mode 2020-09-05 11:45:06 -07:00
Jerry Zhao
ab21c53a42 Add documentation on HarnessBinders 2020-09-04 23:51:36 -07:00
Jerry Zhao
b613c14f1c Fix remaining HarnessBinders bugs 2020-09-04 20:03:12 -07:00
Jerry Zhao
0f50e4d118 Split IOBinders into IOBinders and Harness Binders | punch out clocks to harness for simwidgets and bridges 2020-09-04 15:20:13 -07:00
Jerry Zhao
3258fd8db8 Remove JTAG from firesim comfigs due to @(posedge ~clk) issue 2020-09-03 23:53:51 -07:00
Zitao Fang
0995f1b04b UCode passed all tests 2020-09-02 21:25:36 -07:00
Jerry Zhao
4b30462320 Change default IO set to JTAG+Serial, instead of JTAG+DMI 2020-09-02 20:19:27 -07:00
Zitao Fang
bb1d0a10ae Stage 3 (single port) passed all tests 2020-08-31 18:00:40 -07:00
Jerry Zhao
c8448cc3e1 Bore out a bus clock to drive DebugIO from ChipTop 2020-08-30 18:10:52 -07:00
Zitao Fang
5c5af7bfad Stage 3 passed all tests 2020-08-28 18:37:47 -07:00
Jerry Zhao
17239c56f8 Update AddIOCells.debug comment 2020-08-28 14:36:09 -07:00
Jerry Zhao
27b78f4de2 Only punch realistic subset of DebugIO through chiptop 2020-08-28 14:30:59 -07:00
Jerry Zhao
ee1ce1141c Merge pull request #614 from ucb-bar/diplomatic-clocks
Diplomatic multiclock
2020-08-27 21:09:54 -07:00
Jerry Zhao
239b6b6e09 Bump testchipip 2020-08-27 13:00:43 -07:00
Jerry Zhao
e275a45890 Address PR comments 2020-08-26 12:34:46 -07:00
abejgonzalez
2168813da0 Add help string | Fix emulator CC to not conflict with --vpi 2020-08-21 14:07:32 -07:00
abejgonzalez
c9791ccbdf Update docs | Revert/Update emulator.cc 2020-08-21 12:06:18 -07:00
abejgonzalez
425b8ce850 Add support for multi-threaded verilator 2020-08-20 23:37:17 -07:00
Zitao Fang
b0b09870dd 2-stage core passed all tests 2020-08-17 21:11:44 -07:00
Zitao Fang
84359abd19 Isolated master adapter's TileLink valid signals from the core 2020-08-16 16:07:38 -07:00
Zitao Fang
97f595f415 1-stage passed all tests 2020-08-16 15:41:44 -07:00
Zitao Fang
f6992c61c8 5-stage CPU passed all tests 2020-08-15 00:20:47 -07:00
Zitao Fang
03e50178f1 Add misalignment detection & make M-extension test optional 2020-08-14 16:00:38 -07:00
Zitao Fang
90a7caa323 Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate 2020-08-12 14:27:08 -07:00
Zitao Fang
751215dec1 5-stage core running 2020-08-12 14:26:49 -07:00
Jerry Zhao
abc75e9b95 Fix Reset bug 2020-08-07 17:50:23 -07:00
Zitao Fang
7f5b324d06 Added interrupt 2020-08-05 17:16:36 -07:00