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Stage 3 passed all tests

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This commit is contained in:
Zitao Fang
2020-08-28 18:37:47 -07:00
parent b0b09870dd
commit 5c5af7bfad
2 changed files with 3 additions and 4 deletions
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2
generators/riscv-sodor

Submodule generators/riscv-sodor updated: 602ff66b0e...f2f8795333

5
sims/verilator/Makefile
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@@ -150,9 +150,8 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib)
#########################################################################################
.PRECIOUS: $(output_dir)/%.vpd %.vcd
$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
rm -f $@.vcd && mkfifo $@.vcd
vcd2vpd $@.vcd $@ > /dev/null &
(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
touch $@.vpd
(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v $@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
#########################################################################################
# general cleanup rule