Merge remote-tracking branch 'origin/dev' into serial-tl

generators/chipyard/src/main/scala/Clocks.scala

@@ -58,16 +58,15 @@ object GenerateReset {
     val reset_wire = Wire(Input(Reset()))
     val (reset_io, resetIOCell) = p(GlobalResetSchemeKey) match {
       case GlobalResetSynchronous =>
-        IOCell.generateIOFromSignal(reset_wire, Some("iocell_reset"))
+        IOCell.generateIOFromSignal(reset_wire, "reset")
       case GlobalResetAsynchronousFull =>
-        IOCell.generateIOFromSignal(reset_wire, Some("iocell_reset"), abstractResetAsAsync = true)
+        IOCell.generateIOFromSignal(reset_wire, "reset", abstractResetAsAsync = true)
       case GlobalResetAsynchronous => {
         val async_reset_wire = Wire(Input(AsyncReset()))
         reset_wire := ResetCatchAndSync(clock, async_reset_wire.asBool())
-        IOCell.generateIOFromSignal(async_reset_wire, Some("iocell_reset"), abstractResetAsAsync = true)
+        IOCell.generateIOFromSignal(async_reset_wire, "reset", abstractResetAsAsync = true)
       }
     }
-    reset_io.suggestName("reset")
     chiptop.iocells ++= resetIOCell
     chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => {
       reset_io := th.dutReset
@@ -104,9 +103,8 @@ object ClockingSchemeGenerators {
       //this needs directionality so generateIOFromSignal works
       val clock_wire = Wire(Input(Clock()))
       val reset_wire = GenerateReset(chiptop, clock_wire)
-      val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock"))
+      val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock")
       chiptop.iocells ++= clockIOCell
-      clock_io.suggestName("clock")
 
       implicitClockSourceNode.out.unzip._1.map { o =>
         o.clock := clock_wire
@@ -150,9 +148,8 @@ object ClockingSchemeGenerators {
       // this needs directionality so generateIOFromSignal works
       val clock_wire = Wire(Input(Clock()))
       val reset_wire = GenerateReset(chiptop, clock_wire)
-      val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock"))
+      val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock")
       chiptop.iocells ++= clockIOCell
-      clock_io.suggestName("clock")
       val div_clock = Pow2ClockDivider(clock_wire, 2)
 
       implicitClockSourceNode.out.unzip._1.map { o =>

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -16,7 +16,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
   with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
   with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
-  with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the tilelink-over-serial backing memory
+  with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
   with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
   with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
   with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller

generators/chipyard/src/main/scala/IOBinders.scala

@@ -146,8 +146,7 @@ class WithGPIOCells extends OverrideIOBinder({
 class WithUARTIOCells extends OverrideIOBinder({
   (system: HasPeripheryUARTModuleImp) => {
     val (ports: Seq[UARTPortIO], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
-      val (port, ios) = IOCell.generateIOFromSignal(u, Some(s"iocell_uart_${i}"), system.p(IOCellKey))
-      port.suggestName(s"uart_${i}")
+      val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey))
       (port, ios)
     }).unzip
     (ports, cells2d.flatten)
@@ -158,8 +157,9 @@ class WithUARTIOCells extends OverrideIOBinder({
 class WithSPIIOCells extends OverrideIOBinder({
   (system: HasPeripherySPIFlashModuleImp) => {
     val (ports: Seq[SPIChipIO], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
-      val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(s"spi_${i}")
-      val iocellBase = s"iocell_spi_${i}"
+      val name = s"spi_${i}"
+      val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
+      val iocellBase = s"iocell_${name}"
 
       // SCK and CS are unidirectional outputs
       val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey))
@@ -185,8 +185,7 @@ class WithSPIIOCells extends OverrideIOBinder({
 class WithExtInterruptIOCells extends OverrideIOBinder({
   (system: HasExtInterruptsModuleImp) => {
     if (system.outer.nExtInterrupts > 0) {
-      val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts"), system.p(IOCellKey))
-      port.suggestName("ext_interrupts")
+      val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey))
       (Seq(port), cells)
     } else {
       (Nil, Nil)
@@ -230,19 +229,16 @@ class WithDebugIOCells extends OverrideIOBinder({
 
       // Add IOCells for the DMI/JTAG/APB ports
       val dmiTuple = debug.clockeddmi.map { d =>
-        IOCell.generateIOFromSignal(d, Some("iocell_dmi"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
+        IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
       }
-      dmiTuple.map(_._1).foreach(_.suggestName("dmi"))
 
       val jtagTuple = debug.systemjtag.map { j =>
-        IOCell.generateIOFromSignal(j.jtag, Some("iocell_jtag"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
+        IOCell.generateIOFromSignal(j.jtag, "jtag", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
       }
-      jtagTuple.map(_._1).foreach(_.suggestName("jtag"))
 
       val apbTuple = debug.apb.map { a =>
-        IOCell.generateIOFromSignal(a, Some("iocell_apb"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
+        IOCell.generateIOFromSignal(a, "apb", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
       }
-      apbTuple.map(_._1).foreach(_.suggestName("apb"))
 
       val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq
       (allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq)
@@ -253,8 +249,7 @@ class WithDebugIOCells extends OverrideIOBinder({
 class WithSerialTLIOCells extends OverrideIOBinder({
   (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s =>
     val sys = system.asInstanceOf[BaseSubsystem]
-    val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial_tl"), sys.p(IOCellKey))
-    port.suggestName("serial_tl")
+    val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey))
     (Seq(port), cells)
   }).getOrElse((Nil, Nil))
 })

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -182,7 +182,7 @@ class DividedClockRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
-class LBWIFMemoryRocketConfig extends Config(
+class LBWIFRocketConfig extends Config(
   new testchipip.WithSerialTLMem(isMainMemory=true) ++      // set lbwif memory base to DRAM_BASE, use as main memory
   new freechips.rocketchip.subsystem.WithNoMemPort ++       // remove AXI4 backing memory
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++