wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Bump to the latest Rocket

Browse Source
This commit is contained in:
Zitao Fang
2020-09-09 15:12:37 -07:00
parent fb7804070c
commit 15d53e2cda
2 changed files with 99 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

101
generators/chipyard/src/main/scala/config/SodorConfigs.scala
View File

@@ -4,7 +4,7 @@ import chisel3._
import freechips.rocketchip.config.{Config}
class SodorConfig extends Config(
class Sodor1StageConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithTiedOffDebug ++
@@ -19,6 +19,101 @@ class SodorConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new sodor.common.WithNSodorCores(1) ++
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
new freechips.rocketchip.system.BaseConfig)
class Sodor2StageConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class Sodor3StageConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class Sodor3StageSinglePortConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class Sodor5StageConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class SodorUCodeConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

2
generators/riscv-sodor

Submodule generators/riscv-sodor updated: e635b4ae41...70033f041a