Zitao Fang bb1d0a10ae Stage 3 (single port) passed all tests

2020-08-31 18:00:40 -07:00

..

ariane @ 0ed9107485

Bump Rocketchip to June 2020 for Tile changes

2020-06-18 17:25:31 -07:00

boom @ 859c60553b

Bump boom

2020-06-21 11:56:45 -07:00

chipyard/src/main

Add misalignment detection & make M-extension test optional

2020-08-14 16:00:38 -07:00

firechip/src

Merge pull request #612 from ucb-bar/zynq-target

2020-07-10 18:12:34 -07:00

gemmini @ caaf781ec9

Do not initialize gemmini's onnx-runtime

2020-05-28 12:54:19 -07:00

hwacha @ a989b69759

bump ariane/hwacha/sha3/testchipip/libgloss

2020-05-28 16:11:51 -07:00

icenet @ 705ca50690

get icenet and testchipip unit tests working

2020-04-28 10:32:28 -07:00

nvdla @ b2b78c9f89

NVDLA Integration + Cleanup Ariane Preprocessing (#505)

2020-05-16 12:22:30 -07:00

riscv-sodor @ 477f9a4eb9

Stage 3 (single port) passed all tests

2020-08-31 18:00:40 -07:00

rocket-chip @ 653efa99a2

Bump Rocket-chip again

2020-06-20 12:28:03 -07:00

sha3 @ 762d9d08f8

Bump sha3 for multi-sha fix (#597)

2020-06-05 18:22:31 -07:00

sifive-blocks @ c240e629e2

Override default baud rate for FireChip

2020-07-07 23:00:14 -07:00

sifive-cache @ 4ebefa3e30

sifive cache bump to RC firrtl 1.3

2020-05-12 23:34:01 -07:00

testchipip @ 3366844f50

implement fast loadmem feature

2020-08-01 15:04:18 -07:00

tracegen

Add RANDOM_SEED variable to set random init for VCS and Verilator simulations

2020-07-20 18:25:18 -07:00

utilities/src/main

Bump fesvr for better loadmem impl. Fix verilator loadmem support

2020-08-05 10:05:02 -07:00