Clean up passing ports from IOBinders to HarnessBinders

generators/chipyard/src/main/scala/HarnessBinders.scala

@@ -1,6 +1,7 @@
 package chipyard.harness
 
 import chisel3._
+import chisel3.experimental.{Analog}
 
 import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
@@ -19,6 +20,7 @@ import barstools.iocell.chisel._
 import testchipip._
 
 import chipyard.HasHarnessSignalReferences
+import chipyard.iobinders.ClockedIO
 
 import tracegen.{TraceGenSystemModuleImp}
 import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly}
@@ -33,26 +35,29 @@ case object HarnessBinders extends Field[Map[String, (Any, HasHarnessSignalRefer
 object ApplyHarnessBinders {
   def apply(th: HasHarnessSignalReferences, sys: LazyModule, map: Map[String, (Any, HasHarnessSignalReferences, Seq[Data]) => Seq[Any]], portMap: Map[String, Seq[Data]]) = {
     val pm = portMap.withDefaultValue(Nil)
-    map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s)) }
+    map.map { case (s, f) => f(sys, th, pm(s)) ++ f(sys.module, th, pm(s))
+    }
   }
 }
 
-class OverrideHarnessBinder[T](fn: => (T, HasHarnessSignalReferences, Seq[Data]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
+class OverrideHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
   case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString ->
       ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
+        val pts = ports.map(_.asInstanceOf[S])
         t match {
-          case system: T => fn(system, th, ports)
+          case system: T => fn(system, th, pts)
           case _ => Nil
         }
       })
   )
 })
 
-class ComposeHarnessBinder[T](fn: => (T, HasHarnessSignalReferences, Seq[Data]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
+class ComposeHarnessBinder[T, S <: Data](fn: => (T, HasHarnessSignalReferences, Seq[S]) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
   case HarnessBinders => up(HarnessBinders, site) + (tag.runtimeClass.toString ->
       ((t: Any, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
+        val pts = ports.map(_.asInstanceOf[S])
         t match {
-          case system: T => up(HarnessBinders, site)(tag.runtimeClass.toString)(system, th, ports) ++ fn(system, th, ports)
+          case system: T => up(HarnessBinders, site)(tag.runtimeClass.toString)(system, th, pts) ++ fn(system, th, pts)
           case _ => Nil
         }
       })
@@ -60,109 +65,83 @@ class ComposeHarnessBinder[T](fn: => (T, HasHarnessSignalReferences, Seq[Data])
 })
 
 class WithGPIOTiedOff extends OverrideHarnessBinder({
-  (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    ports.map { case p: GPIOPortIO => p <> AnalogConst(0) }
+  (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Analog]) => {
+    ports.foreach { _ <> AnalogConst(0) }
     Nil
   }
 })
 
 // DOC include start: WithUARTAdapter
 class WithUARTAdapter extends OverrideHarnessBinder({
-  (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    UARTAdapter.connect(ports.map({case p: UARTPortIO => p}))(system.p)
+  (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
+    UARTAdapter.connect(ports)(system.p)
     Nil
   }
 })
 // DOC include end: WithUARTAdapter
 
 class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({
-  (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    SimSPIFlashModel.connect(ports.map({case p: SPIChipIO => p}), th.harnessReset, rdOnly)(system.p)
+  (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => {
+    SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p)
     Nil
   }
 })
 
 class WithSimBlockDevice extends OverrideHarnessBinder({
-  (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    val clock = WireInit(false.B.asClock)
-    ports.map {
-      case p: BlockDeviceIO => SimBlockDevice.connect(clock, th.harnessReset.asBool, Some(p))(system.p)
-      case c: Clock => clock := c
-    }
+  (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => {
+    ports.map { p => SimBlockDevice.connect(p.clock, th.harnessReset.asBool, Some(p.bits))(system.p) }
     Nil
   }
 })
 
 class WithBlockDeviceModel extends OverrideHarnessBinder({
-  (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    val clock = WireInit(false.B.asClock)
-    ports.map {
-      case p: BlockDeviceIO => withClockAndReset(clock, th.harnessReset) { BlockDeviceModel.connect(Some(p))(system.p) }
-      case c: Clock => clock := c
-    }
+  (system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => {
+    ports.map { p => withClockAndReset(p.clock, th.harnessReset) { BlockDeviceModel.connect(Some(p.bits))(system.p) } }
     Nil
   }
 })
 
 class WithLoopbackNIC extends OverrideHarnessBinder({
-  (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    val clock = WireInit(false.B.asClock)
-    ports.map {
-      case p: NICIOvonly => withClockAndReset(clock, th.harnessReset) {
-        NicLoopback.connect(Some(p), system.p(NICKey))
+  (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => {
+    ports.map { p =>
+      withClockAndReset(p.clock, th.harnessReset) {
+        NicLoopback.connect(Some(p.bits), system.p(NICKey))
       }
-      case c: Clock => clock := c
     }
     Nil
   }
 })
 
 class WithSimNetwork extends OverrideHarnessBinder({
-  (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    val clock = WireInit(false.B.asClock)
-    ports.map {
-      case p: NICIOvonly => SimNetwork.connect(Some(p), clock, th.harnessReset.asBool)
-      case c: Clock => clock := c
-    }
+  (system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => {
+    ports.map { p => SimNetwork.connect(Some(p.bits), p.clock, th.harnessReset.asBool) }
     Nil
   }
 })
 
 class WithSimAXIMem extends OverrideHarnessBinder({
-  (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
+  (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => {
     val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
-    val clock = WireInit(false.B.asClock)
-    ports.map {
-      case p: Clock => clock := p
-      case _ =>
-    }
-    val axi4_ports = ports.collect { case p: AXI4Bundle => p }
-    (axi4_ports zip system.memAXI4Node.edges.in).map { case (port: AXI4Bundle, edge) =>
+    (ports zip system.memAXI4Node.edges.in).map { case (port, edge) =>
       val mem = LazyModule(new SimAXIMem(edge, size=p(ExtMem).get.master.size)(p))
-      withClockAndReset(clock, th.harnessReset) {
+      withClockAndReset(port.clock, th.harnessReset) {
         Module(mem.module).suggestName("mem")
       }
-      mem.io_axi4.head <> port
+      mem.io_axi4.head <> port.bits
     }
     Nil
   }
 })
 
 class WithBlackBoxSimMem extends OverrideHarnessBinder({
-  (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
+  (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => {
     val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
-    val clock = WireInit(false.B.asClock)
-    ports.map {
-      case p: Clock => clock := p
-      case _ =>
-    }
-    val axi4_ports = ports.collect { case p: AXI4Bundle => p }
-    (axi4_ports zip system.memAXI4Node.edges.in).map { case (port: AXI4Bundle, edge) =>
+    (ports zip system.memAXI4Node.edges.in).map { case (port, edge) =>
       val memSize = p(ExtMem).get.master.size
       val lineSize = p(CacheBlockBytes)
       val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)).suggestName("simdram")
-      mem.io.axi <> port
-      mem.io.clock := clock
+      mem.io.axi <> port.bits
+      mem.io.clock := port.clock
       mem.io.reset := th.harnessReset
     }
     Nil
@@ -170,57 +149,44 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({
 })
 
 class WithSimAXIMMIO extends OverrideHarnessBinder({
-  (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
+  (system: CanHaveMasterAXI4MMIOPort, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => {
     val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
-    val clock = WireInit(false.B.asClock)
-    ports.map {
-       case p: Clock => clock := p
-       case _ =>
-    }
-    val axi4_ports = ports.collect { case p: AXI4Bundle => p }
-    (axi4_ports zip system.mmioAXI4Node.edges.in).map { case (port: AXI4Bundle, edge) =>
+    (ports zip system.mmioAXI4Node.edges.in).map { case (port, edge) =>
       val mmio_mem = LazyModule(new SimAXIMem(edge, size = p(ExtBus).get.size)(p))
-      withClockAndReset(clock, th.harnessReset) {
+      withClockAndReset(port.clock, th.harnessReset) {
         Module(mmio_mem.module).suggestName("mmio_mem")
       }
-      mmio_mem.io_axi4.head <> port
+      mmio_mem.io_axi4.head <> port.bits
     }
     Nil
   }
 })
 
 class WithTieOffInterrupts extends OverrideHarnessBinder({
-  (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    ports.map { case p: UInt =>  p := 0.U }
+  (system: HasExtInterruptsModuleImp, th: HasHarnessSignalReferences, ports: Seq[UInt]) => {
+    ports.foreach { _ := 0.U }
     Nil
   }
 })
 
 class WithTieOffL2FBusAXI extends OverrideHarnessBinder({
-  (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    ports.map {
-      case p: AXI4Bundle =>
-        p := DontCare
-        p.tieoff()
-      case c: Clock =>
-    }
+  (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => {
+    ports.foreach({ p => p := DontCare; p.bits.tieoff() })
     Nil
   }
 })
 
 class WithSimDebug extends OverrideHarnessBinder({
   (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    if (!ports.isEmpty) {
-      val dtm_success = Wire(Bool())
-      when (dtm_success) { th.success := true.B }
-      ports.map {
-        case d: ClockedDMIIO =>
-          val dtm = Module(new SimDTM()(system.p)).connect(th.harnessClock, th.harnessReset.asBool, d, dtm_success)
-        case j: JTAGIO =>
-          val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success)
-        case _ =>
-          require(false, "We only support DMI or JTAG simulated debug connections")
-      }
+    ports.map {
+      case d: ClockedDMIIO =>
+        val dtm_success = WireInit(false.B)
+        when (dtm_success) { th.success := true.B }
+        val dtm = Module(new SimDTM()(system.p)).connect(th.harnessClock, th.harnessReset.asBool, d, dtm_success)
+      case j: JTAGIO =>
+        val dtm_success = WireInit(false.B)
+        when (dtm_success) { th.success := true.B }
+        val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success)
     }
     Nil
   }
@@ -229,63 +195,56 @@ class WithSimDebug extends OverrideHarnessBinder({
 class WithTiedOffDebug extends OverrideHarnessBinder({
   (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
     ports.map {
+      case j: JTAGIO =>
+        j.TCK := true.B.asClock
+        j.TMS := true.B
+        j.TDI := true.B
+        j.TRSTn.foreach { r => r := true.B }
       case d: ClockedDMIIO =>
         d.dmi.req.valid := false.B
         d.dmi.req.bits  := DontCare
         d.dmi.resp.ready := true.B
         d.dmiClock := false.B.asClock
         d.dmiReset := true.B
-      case j: JTAGIO =>
-        j.TCK := true.B.asClock
-        j.TMS := true.B
-        j.TDI := true.B
-        j.TRSTn.foreach { r => r := true.B }
       case a: ClockedAPBBundle =>
         a.tieoff()
         a.clock := false.B.asClock
         a.reset := true.B.asAsyncReset
         a.psel := false.B
         a.penable := false.B
-      case _ => require(false)
     }
     Nil
   }
 })
 
+
 class WithTiedOffSerial extends OverrideHarnessBinder({
-  (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    ports.map {
-      case p: SerialIO => SerialAdapter.tieoff(Some(p))
-      case _ =>
-    }
+  (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
+    ports.map { p => SerialAdapter.tieoff(Some(p.bits)) }
     Nil
   }
 })
 
 class WithSimSerial extends OverrideHarnessBinder({
-  (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    val serial_clock = WireInit(false.B.asClock)
-    ports.map {
-      case p: SerialIO =>
-        val ser_success = SerialAdapter.connectSimSerial(p, serial_clock, th.harnessReset)
-        when (ser_success) { th.success := true.B }
-      case c: Clock =>
-        serial_clock := c
+  (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
+    ports.map { p =>
+      val ser_success = SerialAdapter.connectSimSerial(p.bits, p.clock, th.harnessReset)
+      when (ser_success) { th.success := true.B }
     }
     Nil
   }
 })
 
 class WithTraceGenSuccess extends OverrideHarnessBinder({
-  (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    ports.map { case p: Bool => when (p) { th.success := true.B } }
+  (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => {
+    ports.map { p => when (p) { th.success := true.B } }
     Nil
   }
 })
 
 class WithSimDromajoBridge extends ComposeHarnessBinder({
-  (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
-    ports.map { case p: TraceOutputTop => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) }
+  (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => {
+    ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) }
     Nil
   }
 })

generators/chipyard/src/main/scala/IOBinders.scala

@@ -74,7 +74,7 @@ object GetSystemParameters {
 
 // This macro overrides previous matches on some Top mixin. This is useful for
 // binders which drive IO, since those typically cannot be composed
-class OverrideIOBinder[T](fn: => (T) => (Seq[Data], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
+class OverrideIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
   case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString ->
       ((t: Any) => {
         t match {
@@ -87,7 +87,7 @@ class OverrideIOBinder[T](fn: => (T) => (Seq[Data], Seq[IOCell]))(implicit tag:
 
 // This macro composes with previous matches on some Top mixin. This is useful for
 // annotation-like binders, since those can typically be composed
-class ComposeIOBinder[T](fn: => (T) => (Seq[Data], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
+class ComposeIOBinder[T, S <: Data](fn: => (T) => (Seq[S], Seq[IOCell]))(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
   case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString ->
       ((t: Any) => {
         t match {
@@ -116,6 +116,11 @@ object BoreHelper {
 
 case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams())
 
+class ClockedIO[T <: Data](gen: T) extends Bundle {
+  val clock = Output(Clock())
+  val bits = gen
+  override def cloneType: this.type = (new ClockedIO(DataMirror.internal.chiselTypeClone[T](gen))).asInstanceOf[this.type]
+}
 
 class WithGPIOCells extends OverrideIOBinder({
   (system: HasPeripheryGPIOModuleImp) => {
@@ -131,14 +136,15 @@ class WithGPIOCells extends OverrideIOBinder({
         (g, iocell)
       }).unzip
     }).unzip
-    (ports2d.flatten, cells2d.flatten)
+    val ports: Seq[Analog] = ports2d.flatten
+    (ports, cells2d.flatten)
   }
 })
 
 // DOC include start: WithUARTIOCells
 class WithUARTIOCells extends OverrideIOBinder({
   (system: HasPeripheryUARTModuleImp) => {
-    val (ports, cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
+    val (ports: Seq[UARTPortIO], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
       val (port, ios) = IOCell.generateIOFromSignal(u, Some(s"iocell_uart_${i}"), system.p(IOCellKey))
       port.suggestName(s"uart_${i}")
       (port, ios)
@@ -150,7 +156,7 @@ class WithUARTIOCells extends OverrideIOBinder({
 
 class WithSPIIOCells extends OverrideIOBinder({
   (system: HasPeripherySPIFlashModuleImp) => {
-    val (ports, cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
+    val (ports: Seq[SPIChipIO], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
       val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(s"spi_${i}")
       val iocellBase = s"iocell_spi_${i}"
 
@@ -178,7 +184,7 @@ class WithSPIIOCells extends OverrideIOBinder({
 class WithExtInterruptIOCells extends OverrideIOBinder({
   (system: HasExtInterruptsModuleImp) => {
     if (system.outer.nExtInterrupts > 0) {
-      val (port, cells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts"), system.p(IOCellKey))
+      val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts"), system.p(IOCellKey))
       port.suggestName("ext_interrupts")
       (Seq(port), cells)
     } else {
@@ -246,94 +252,79 @@ class WithDebugIOCells extends OverrideIOBinder({
 class WithSerialIOCells extends OverrideIOBinder({
   (system: CanHavePeripherySerial) => system.serial.map({ s =>
     val sys = system.asInstanceOf[BaseSubsystem]
-    val (port, cells) = IOCell.generateIOFromSignal(s, Some("iocell_serial"), sys.p(IOCellKey))
-    val serial_clock = Wire(Output(Clock())).suggestName("chiptop_serial_clock")
-    serial_clock := false.B.asClock // necessary for BoringUtils to work properly
-    dontTouch(serial_clock)
-    BoringUtils.bore(sys.fbus.module.clock, Seq(serial_clock))
-    val (serial_clock_io, serial_clock_cell) = IOCell.generateIOFromSignal(serial_clock, Some("serial_clock"), sys.p(IOCellKey))
-    serial_clock_io.suggestName("serial_clock")
+    val clocked_serial = Wire(new ClockedIO(DataMirror.internal.chiselTypeClone[SerialIO](s))).suggestName("serial_wire")
+    clocked_serial.clock := BoreHelper("serial_clock", sys.fbus.module.clock)
+    clocked_serial.bits <> s
+    val (port, cells) = IOCell.generateIOFromSignal(clocked_serial, Some("serial"), sys.p(IOCellKey))
     port.suggestName("serial")
-    (Seq(port, serial_clock_io), cells ++ serial_clock_cell)
+    (Seq(port), cells)
   }).getOrElse((Nil, Nil))
 })
 
 
 class WithAXI4MemPunchthrough extends OverrideIOBinder({
   (system: CanHaveMasterAXI4MemPort) => {
-    val clock = if (!system.mem_axi4.isEmpty) {
-      Some(BoreHelper("axi4_mem_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock))
-    } else {
-      None
-    }
-    val ports = system.mem_axi4.zipWithIndex.map({ case (m, i) =>
-      val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName(s"axi4_mem_${i}")
-      p <> m
+    val ports: Seq[ClockedIO[AXI4Bundle]] = system.mem_axi4.zipWithIndex.map({ case (m, i) =>
+      val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}")
+      p.bits <> m
+      p.clock := BoreHelper("axi4_mem_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock)
       p
     })
-    (ports ++ clock, Nil)
+    (ports, Nil)
   }
 })
 
 class WithAXI4MMIOPunchthrough extends OverrideIOBinder({
   (system: CanHaveMasterAXI4MMIOPort) => {
-    val clock = if (!system.mmio_axi4.isEmpty) {
-      Some(BoreHelper("axi4_mmio_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock))
-    } else {
-      None
-    }
-    val ports = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>
-      val p = IO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)).suggestName(s"axi4_mmio_${i}")
-      p <> m
+    val ports: Seq[ClockedIO[AXI4Bundle]] = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>
+      val p = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}")
+      p.bits <> m
+      p.clock := BoreHelper("axi4_mmio_clock", system.asInstanceOf[BaseSubsystem].mbus.module.clock)
       p
     })
-    (ports ++ clock, Nil)
+    (ports, Nil)
   }
 })
 
 class WithL2FBusAXI4Punchthrough extends OverrideIOBinder({
    (system: CanHaveSlaveAXI4Port) => {
-    val clock = if (!system.l2_frontend_bus_axi4.isEmpty) {
-      Some(BoreHelper("axi4_fbus_clock", system.asInstanceOf[BaseSubsystem].fbus.module.clock))
-    } else {
-      None
-    }
-    val ports = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) =>
-      val p = IO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_fbus_${i}")
-      m <> p
+    val ports: Seq[ClockedIO[AXI4Bundle]] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) =>
+      val p = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}")
+      m <> p.bits
+      p.clock := BoreHelper("axi4_fbus_clock", system.asInstanceOf[BaseSubsystem].fbus.module.clock)
       p
     })
-    (ports ++ clock, Nil)
+    (ports, Nil)
   }
 })
 
 class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({
   (system: CanHavePeripheryBlockDeviceModuleImp) => {
-    val ports = system.bdev.map({ bdev =>
-      val p = IO(new BlockDeviceIO()(system.p)).suggestName("blockdev")
-      val clock = BoreHelper("blkdev_clk", system.outer.controller.get.module.clock)
-      p <> bdev
-      Seq(p, clock)
-    }).getOrElse(Nil)
+    val ports: Seq[ClockedIO[BlockDeviceIO]] = system.bdev.map({ bdev =>
+      val p = IO(new ClockedIO(new BlockDeviceIO()(system.p))).suggestName("blockdev")
+      p.clock := BoreHelper("blkdev_clk", system.outer.controller.get.module.clock)
+      p.bits <> bdev
+      p
+    }).toSeq
     (ports, Nil)
   }
 })
 
 class WithNICIOPunchthrough extends OverrideIOBinder({
   (system: CanHavePeripheryIceNICModuleImp) => {
-    val port = system.net.map({ n =>
-      val p = IO(new NICIOvonly).suggestName("nic")
-      val clock = BoreHelper("nic_clk", system.outer.icenicOpt.get.module.clock)
-      p <> n
-      Seq(p, clock)
-    }).getOrElse(Nil)
-    (port.toSeq, Nil)
+    val ports: Seq[ClockedIO[NICIOvonly]] = system.net.map({ n =>
+      val p = IO(new ClockedIO(new NICIOvonly)).suggestName("nic")
+      p.clock := BoreHelper("nic_clk", system.outer.icenicOpt.get.module.clock)
+      p.bits <> n
+      p
+    }).toSeq
+    (ports, Nil)
   }
 })
 
 class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({
   (system: TraceGenSystemModuleImp) => {
-    val success = IO(Output(Bool())).suggestName("success")
+    val success: Bool = IO(Output(Bool())).suggestName("success")
     success := system.success
     (Seq(success), Nil)
   }
@@ -341,7 +332,7 @@ class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({
 
 class WithTraceIOPunchthrough extends OverrideIOBinder({
   (system: CanHaveTraceIOModuleImp) => {
-    val ports = system.traceIO.map { t =>
+    val ports: Option[TraceOutputTop] = system.traceIO.map { t =>
       val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace")
       trace <> t
       trace