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Deprecate support for on-chip SerialAdapter

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This commit is contained in:
Jerry Zhao
2020-09-14 19:41:02 -07:00
parent f9cc1dc2c2
commit 0d8e87126c
11 changed files with 29 additions and 66 deletions
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1
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -17,7 +17,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the tilelink-over-serial backing memory
with testchipip.CanHavePeripheryTSISerial // Enables optionally adding the TSI serial-adapter and port
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller

50
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -223,47 +223,23 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
})
class WithTiedOffTSISerial extends OverrideHarnessBinder({
(system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { p => SerialAdapter.tieoff(Some(p.bits)) }
Nil
}
})
class WithSimTSISerial extends OverrideHarnessBinder({
(system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { p =>
val ser_success = SerialAdapter.connectSimSerial(p.bits, p.clock, th.harnessReset)
when (ser_success) { th.success := true.B }
}
Nil
}
})
class WithSimTLSerial(withHarnessSerialAdapter: Boolean = false) extends OverrideHarnessBinder({
class WithSerialAdapterTiedOff extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
withClockAndReset(port.clock, th.harnessReset) {
val lRam = LazyModule(new SerialRAM(
p(SerialTLKey).get.width,
p(SerialTLKey).get.memParams.master.size,
p(SerialTLKey).get.memParams.master.base,
managerEdge = system.serdesser.get.managerNode.edges.in(0),
clientEdge = system.serdesser.get.clientNode.edges.out(0)
))
val ram = Module(lRam.module)
ram.io.ser <> port.bits
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
SerialAdapter.tieoff(ram.module.io.tsi_ser)
})
}
})
require(lRam.serdesser.module.mergedParams == system.serdesser.get.module.mergedParams,
"Mismatch between chip-side diplomatic params and testram diplomatic params")
if (withHarnessSerialAdapter) {
val success = SerialAdapter.connectSimSerial(Some(ram.io.tsi_ser), port.clock, th.harnessReset.asBool)
when (success) { th.success := true.B }
} else {
SerialAdapter.tieoff(Some(ram.io.tsi_ser))
}
}
class WithSimSerial extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, port.clock, th.harnessReset.asBool)
when (success) { th.success := true.B }
})
}
})

9
generators/chipyard/src/main/scala/IOBinders.scala
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@@ -250,15 +250,6 @@ class WithDebugIOCells extends OverrideIOBinder({
}
})
class WithSerialTSIIOCells extends OverrideIOBinder({
(system: CanHavePeripheryTSISerial) => system.serial_tsi.map({ s =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial_tsi"), sys.p(IOCellKey))
port.suggestName("serial_tsi")
(Seq(port), cells)
}).getOrElse((Nil, Nil))
})
class WithSerialTLIOCells extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s =>
val sys = system.asInstanceOf[BaseSubsystem]

4
generators/chipyard/src/main/scala/Subsystem.scala
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@@ -25,12 +25,12 @@ import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile}
import testchipip.{DromajoHelper, CanHavePeripheryTSISerial, SerialTSIKey}
import testchipip.{DromajoHelper, CanHavePeripheryTLSerial, SerialTLKey}
trait CanHaveHTIF { this: BaseSubsystem =>
// Advertise HTIF if system can communicate with fesvr
if (this match {
case _: CanHavePeripheryTSISerial if p(SerialTSIKey).nonEmpty => true
case _: CanHavePeripheryTKSerial if p(SerialTLKey).nonEmpty => true
case _: HasPeripheryDebug if p(ExportDebug).dmi => true
case _ => false
}) {

6
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -14,8 +14,8 @@ class AbstractConfig extends Config(
// The HarnessBinders control generation of hardware in the TestHarness
new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present
new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
new chipyard.harness.WithSimSerial ++ // add external serial-adapter and RAM
new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled
new chipyard.harness.WithSimTSISerial ++ // add SimSerial adapter for HTIF, if serial port is present
new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present
new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled
new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled
@@ -29,7 +29,6 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++
new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++
new chipyard.iobinders.WithNICIOPunchthrough ++
new chipyard.iobinders.WithSerialTSIIOCells ++
new chipyard.iobinders.WithSerialTLIOCells ++
new chipyard.iobinders.WithDebugIOCells ++
new chipyard.iobinders.WithUARTIOCells ++
@@ -39,8 +38,7 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithTraceIOPunchthrough ++
new chipyard.iobinders.WithExtInterruptIOCells ++
new testchipip.WithSerialTSI ++ // use testchipip serial offchip link
new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs

2
generators/chipyard/src/main/scala/config/ArianeConfigs.scala
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@@ -13,7 +13,7 @@ class ArianeConfig extends Config(
new chipyard.config.AbstractConfig)
class dmiArianeConfig extends Config(
new chipyard.harness.WithTiedOffTSISerial ++ // Tie off the serial port, override default instantiation of SimSerial
new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new ariane.WithNArianeCores(1) ++ // single Ariane core
new chipyard.config.AbstractConfig)

10
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -25,7 +25,7 @@ class GemminiRocketConfig extends Config(
// DOC include start: DmiRocket
class dmiRocketConfig extends Config(
new chipyard.harness.WithTiedOffTSISerial ++ // don't use serial to drive the chip, since we use DMI instead
new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
@@ -182,10 +182,8 @@ class DividedClockRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class TLSerialRocketConfig extends Config(
new chipyard.harness.WithSimTLSerial(withHarnessSerialAdapter = true) ++ // add external TL backing memory, and external serial adapter
new testchipip.WithDefaultSerialTL ++ // support tilelink-over-serial
new testchipip.WithNoSerialTSI ++ // remove internal serial adapter
class LBWIFMemoryRocketConfig extends Config(
new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
new chipyard.config.AbstractConfig)

5
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -66,10 +66,11 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
})
class WithSerialBridge extends OverrideHarnessBinder({
(system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { p =>
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, p, th.harnessReset)
withClockAndReset(p.clock, th.harnessReset) {
SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system))
SerialBridge(p.clock, ram.module.io.tsi_ser, MainMemoryConsts.globalName)(GetSystemParameters(system))
}
}
Nil

4
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -84,7 +84,7 @@ class WithFireSimConfigTweaks extends Config(
// Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
// for signalling simulation termination under simulation success. This fragment can
// be removed if you supply an auxiliary bridge that signals simulation termination
new testchipip.WithSerialTSI ++
new testchipip.WithDefaultSerialTL ++
// Optional: Removing this will require using an initramfs under linux
new testchipip.WithBlockDevice ++
// Required*: Scale default baud rate with periphery bus frequency
@@ -131,7 +131,7 @@ class FireSimSmallSystemConfig extends Config(
new WithoutClockGating ++
new WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
new testchipip.WithSerialTSI ++
new testchipip.WithDefaultSerialTL ++
new testchipip.WithBlockDevice ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++

2
generators/testchipip

Submodule generators/testchipip updated: 6f81573754...e845cb3f50

2
tools/barstools

Submodule tools/barstools updated: 31590a7948...847f72eca0