Only punch realistic subset of DebugIO through chiptop
This commit is contained in:
Jerry Zhao
@@ -7,6 +7,7 @@ import chisel3.experimental.{Analog, IO}
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import freechips.rocketchip.config.{Field, Config, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.jtag.{JTAGIO}
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.system.{SimAXIMem}
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import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
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@@ -163,30 +164,65 @@ object AddIOCells {
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}
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/**
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* Add IO cells to a debug module and name the IO ports.
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* @param psd A PSDIO bundle
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* Add IO cells to a debug module and name the IO ports, for debug IO which must go off-chip
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* For on-chip debug IO, drive them appropriately
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* @param system A BaseSubsystem that might have a debug module
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* @param resetctrlOpt An optional ResetCtrlIO bundle
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* @param debugOpt An optional DebugIO bundle
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* @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references)
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* @return Returns a tuple2 of (Generated debug io ports, Generated IOCells)
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*/
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def debug(psd: PSDIO, resetctrlOpt: Option[ResetCtrlIO], debugOpt: Option[DebugIO])(implicit p: Parameters):
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(PSDIO, Option[ResetCtrlIO], Option[DebugIO], Seq[IOCell]) = {
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val (psdPort, psdIOs) = IOCell.generateIOFromSignal(
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psd, Some("iocell_psd"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
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val debugTuple = debugOpt.map(d =>
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IOCell.generateIOFromSignal(d, Some("iocell_debug"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync))
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val debugPortOpt: Option[DebugIO] = debugTuple.map(_._1)
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val debugIOs: Seq[IOCell] = debugTuple.map(_._2).toSeq.flatten
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debugPortOpt.foreach(_.suggestName("debug"))
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def debug(system: HasPeripheryDebugModuleImp)(implicit p: Parameters): (Seq[Bundle], Seq[IOCell]) = {
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system.debug.map { debug =>
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val resetctrlTuple = resetctrlOpt.map(d =>
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IOCell.generateIOFromSignal(d, Some("iocell_resetctrl"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync))
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val resetctrlPortOpt: Option[ResetCtrlIO] = resetctrlTuple.map(_._1)
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val resetctrlIOs: Seq[IOCell] = resetctrlTuple.map(_._2).toSeq.flatten
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resetctrlPortOpt.foreach(_.suggestName("resetctrl"))
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// We never use the PSDIO, so tie it off on-chip
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system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
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psdPort.suggestName("psd")
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(psdPort, resetctrlPortOpt, debugPortOpt, psdIOs ++ debugIOs ++ resetctrlIOs)
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// Set resetCtrlOpt with the system reset
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system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := system.reset.asBool } }
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system.debug.map { d =>
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// Tie off extTrigger
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d.extTrigger.foreach { t =>
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t.in.req := false.B
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t.out.ack := t.out.req
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}
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// Tie off disableDebug
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d.disableDebug.foreach { d => d := false.B }
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// Drive JTAG on-chip IOs
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d.systemjtag.map { j =>
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j.reset := system.reset
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j.mfr_id := system.p(JtagDTMKey).idcodeManufId.U(11.W)
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j.part_number := system.p(JtagDTMKey).idcodePartNum.U(16.W)
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j.version := system.p(JtagDTMKey).idcodeVersion.U(4.W)
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}
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}
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// Connect DebugClockAndReset to system implicit clock. TODO this should use the clock of the bus the debug module is attached to
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Debug.connectDebugClockAndReset(Some(debug), system.clock)(system.p)
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// Add IOCells for the DMI/JTAG/APB ports
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val dmiTuple = debug.clockeddmi.map { d =>
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IOCell.generateIOFromSignal(d, Some("iocell_dmi"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
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}
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dmiTuple.map(_._1).foreach(_.suggestName("dmi"))
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val jtagTuple = debug.systemjtag.map { j =>
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IOCell.generateIOFromSignal(j.jtag, Some("iocell_jtag"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
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}
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jtagTuple.map(_._1).foreach(_.suggestName("jtag"))
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val apbTuple = debug.apb.map { a =>
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IOCell.generateIOFromSignal(a, Some("iocell_apb"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
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}
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apbTuple.map(_._1).foreach(_.suggestName("apb"))
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val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq
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(allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq)
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}.getOrElse((Nil, Nil))
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}
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/**
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@@ -364,40 +400,53 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({
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}
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})
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// TODO we need to rethink what "Tie-off-debug" means. The current system punches out
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// excessive IOs.
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class WithTiedOffDebug extends OverrideIOBinder({
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class WithSimDebug extends OverrideIOBinder({
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(system: HasPeripheryDebugModuleImp) => {
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val (psdPort, resetctrlOpt, debugPortOpt, ioCells) =
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AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p)
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val (ports, iocells) = AddIOCells.debug(system)(system.p)
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val harnessFn = (th: HasHarnessSignalReferences) => {
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Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p)
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// tieoffDebug doesn't actually tie everything off :/
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debugPortOpt.foreach { d =>
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d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare; cdmi.dmiClock := th.harnessClock })
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d.dmactiveAck := DontCare
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d.clock := th.harnessClock // TODO fix: This should be driven from within the chip
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val dtm_success = Wire(Bool())
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when (dtm_success) { th.success := true.B }
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ports.map {
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case d: ClockedDMIIO =>
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val dtm = Module(new SimDTM()(system.p)).connect(th.harnessClock, th.harnessReset.asBool, d, dtm_success)
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case j: JTAGIO =>
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val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success)
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case _ =>
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require(false, "We only support DMI or JTAG simulated debug connections")
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}
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Nil
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}
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Seq((Seq(psdPort) ++ resetctrlOpt ++ debugPortOpt.toSeq, Nil, Some(harnessFn)))
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Seq((ports, iocells, Some(harnessFn)))
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}
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})
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// TODO we need to rethink what this does. The current system punches out excessive IOs.
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// Some of the debug clock/reset should be driven from on-chip
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class WithSimDebug extends OverrideIOBinder({
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class WithTiedOffDebug extends OverrideIOBinder({
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(system: HasPeripheryDebugModuleImp) => {
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val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) =
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AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p)
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val (ports, iocells) = AddIOCells.debug(system)(system.p)
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val harnessFn = (th: HasHarnessSignalReferences) => {
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val dtm_success = Wire(Bool())
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Debug.connectDebug(debugPortOpt, resetctrlPortOpt, psdPort, th.harnessClock, th.harnessReset.asBool, dtm_success)(system.p)
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when (dtm_success) { th.success := true.B }
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th.dutReset := th.harnessReset.asBool | debugPortOpt.map { debug => AsyncResetReg(debug.ndreset).asBool }.getOrElse(false.B)
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ports.map {
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case d: ClockedDMIIO =>
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d.dmi.req.valid := false.B
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d.dmi.req.bits := DontCare
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d.dmi.resp.ready := true.B
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d.dmiClock := th.harnessClock
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d.dmiReset := th.harnessReset
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case j: JTAGIO =>
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j.TCK := true.B.asClock
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j.TMS := true.B
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j.TDI := true.B
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j.TRSTn.foreach { r => r := true.B }
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case a: ClockedAPBBundle =>
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a.tieoff()
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a.clock := false.B.asClock
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a.reset := true.B.asAsyncReset
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a.psel := false.B
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a.penable := false.B
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case _ => require(false)
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}
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Nil
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}
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Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn)))
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Seq((ports, iocells, Some(harnessFn)))
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}
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})
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