Cores now have an extra CoreParam, useSupervisor which was set to
the default false. Whether a core has supervisor mode is the union
of this and useVM which defaults true so not change was made by this
addition.
BusTopologies are now set with the Config system rather than a system
mixin and so all configs now include the config most similar to the
previous mixin
Testchipip was updated to be able to replace the systembus, in this
new config system, with a ring bus.
The L2 cache repo needed a similar update on how to find the buses.
It currently points to the ucb-bar fork
Treadle is bumped to its release branch
[WIP] Minimally elaborating design
Bring up a feature-complete Chipyard stage
Pull in Makefrag generation; Bump submodules
Update config generation, and global reset scheme
Bump submodules; clean up
Bump FireSim
Remove some unhygenic comments / WS
Remove the rocketchip subproject
[CI] Lengthen ariane tests timeout
Address some remaining reviewer comments
[firechip] Refresh a Field that cannot be used across repeated instantiations
Bump all submodules
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success).
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem.
* BuildTop now builds a ChipTop dut module in the TestHarness by default
* A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions).
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation.
* The default for the TOP make variable is now ChipTop (was Top)
* [make] split up specific make vars/targets into frags
* [make] move dramsim and max-cycles into SIM_FLAGS
* [misc] move ariane configs to configs/ folder
* [ariane/make] integrate ariane | have verilator be installed on path not in makefile
* [misc] warn on verilator not found | search for v files | cleanup build.sbt + .gitignore
* [firesim] bump
* [ci] add midas ariane tests
* [docker/ci] use new docker-image with verilator | re-elab on v changes for ariane | address comments
* [ci] remove references to local verilator install
* [verilator] update flags
* [verilator] minimal set of flags for ariane
* [ariane] bump ariane to master
* [ci] revert to 4.016 verilator
* [ci] install verilator to ci server | misc compile fixes
* [ci/make] add longer ci timeout | update when assert is added in verilator sim
* [firesim] bump for misc. updates
* [make/ci] cleanup makefile and remove firesim tests of it
* [docs/firesim] bump and clean docs
* [firesim] bump
* [ci] use remote verilator for midas tests
* [misc] cleanup built.sbt more
* [firesim] bump
* [misc] bump build.sbt patch for tutorials
* [firesim/ci] cleanup and bump firesim
