David Biancolin 59dd6a79ff [firechip] Enable trace by default in BOOM-based targets (#412) ...

* [firechip] Enable trace by default in BOOM-based targets

* Bump boom for trace enchancements

2020-01-30 15:26:00 -08:00

..

boom @ 1d4d0cda50

[firechip] Enable trace by default in BOOM-based targets (#412)

2020-01-30 15:26:00 -08:00

example/src/main

[example] fix multi-rocc boom+rocket+hwacha config (#413)

2020-01-28 16:39:39 -08:00

firechip/src

[firechip] Enable trace by default in BOOM-based targets (#412)

2020-01-30 15:26:00 -08:00

gemmini @ 6602434b34

Bump gemmini and the Spike simulator in esp-tools (#394)

2020-01-23 17:06:09 -08:00

hwacha @ ef5e5196b6

Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

2019-12-12 13:39:09 -08:00

icenet @ 49b6dfb634

bump icenet to master branch commit

2020-01-23 19:01:40 -08:00

rocket-chip @ 4f0cdea85c

Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

2019-12-12 13:39:09 -08:00

sha3 @ 543adb4ff1

bump sha3 and testchipip (#398)

2020-01-23 18:36:56 -08:00

sifive-blocks @ 1bc0ef18d6

Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

2019-12-12 13:39:09 -08:00

sifive-cache @ d3d95ece5a

bump sifive-cache for updated gitignore (#411)

2020-01-28 15:35:18 -08:00

testchipip @ c11549ba30

bump sha3 and testchipip (#398)

2020-01-23 18:36:56 -08:00

tracegen/src/main/scala

[tracegen] Add tracegen support for the BOOM L1D (#362)

2020-01-23 16:01:32 -08:00

utilities/src/main

Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

2019-12-12 13:39:09 -08:00