[firechip] Enable trace by default in BOOM-based targets (#412)

* [firechip] Enable trace by default in BOOM-based targets

* Bump boom for trace enchancements

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -80,6 +80,10 @@ class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => {
   ))
 })
 
+class WithBoomEnableTrace extends Config((site, here, up) => {
+  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+})
+
 // Disables clock-gating; doesn't play nice with our FAME-1 pass
 class WithoutClockGating extends Config((site, here, up) => {
   case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
@@ -176,6 +180,7 @@ class FireSimBoomConfig extends Config(
   new WithNICKey ++
   new WithSerial ++
   new WithBlockDevice ++
+  new WithBoomEnableTrace ++
   new WithBoomL2TLBs(1024) ++
   new WithoutClockGating ++
   new WithDefaultMemModel ++

generators/firechip/src/main/scala/TargetMixins.scala

@@ -45,7 +45,7 @@ trait HasTraceIOImp extends LazyModuleImp {
   // Enabled to test TracerV trace capture
   if (p(PrintTracePort)) {
     val traceprint = Wire(UInt(512.W))
-    traceprint := Cat(traceIO.traces.map(_.asUInt))
+    traceprint := Cat(traceIO.traces.map(_.reverse.asUInt))
     printf("TRACEPORT: %x\n", traceprint)
   }
 }