Ariane Integration (#448)

* [ariane/make] integrate ariane | have verilator be installed on path not in makefile

* [misc] warn on verilator not found | search for v files | cleanup build.sbt + .gitignore

* [firesim] bump

* [ci] add midas ariane tests

* [docker/ci] use new docker-image with verilator | re-elab on v changes for ariane | address comments

* [ci] remove references to local verilator install

* [verilator] update flags

* [verilator] minimal set of flags for ariane

* [ariane] bump ariane to master

* [ci] revert to 4.016 verilator

* [ci] install verilator to ci server | misc compile fixes

* [ci/make] add longer ci timeout | update when assert is added in verilator sim

* [firesim] bump for misc. updates

* [make/ci] cleanup makefile and remove firesim tests of it

* [docs/firesim] bump and clean docs

* [firesim] bump

* [ci] use remote verilator for midas tests

* [misc] cleanup built.sbt more

* [firesim] bump

* [misc] bump build.sbt patch for tutorials

* [firesim/ci] cleanup and bump firesim

generators/chipyard/src/main/scala/ArianeConfigs.scala

@@ -0,0 +1,42 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+// ---------------------
+// Ariane Configs
+// ---------------------
+
+class ArianeConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
+  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
+  new chipyard.iobinders.WithSimAXIMem ++                        // drive the master AXI4 memory with a SimAXIMem
+  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
+  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
+  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
+  new chipyard.config.WithNoGPIO ++                              // no top-level GPIO pins (overrides default set in sifive-blocks)
+  new chipyard.config.WithBootROM ++                             // use default bootrom
+  new chipyard.config.WithUART ++                                // add a UART
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
+  new ariane.WithNArianeCores(1) ++                              // single Ariane core
+  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
+
+class dmiArianeConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithTiedOffSerial ++
+  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new ariane.WithNArianeCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)

generators/chipyard/src/main/scala/Generator.scala

@@ -14,6 +14,7 @@ object Generator extends GeneratorApp {
     implicit val p: Parameters = params
     TestSuiteHelper.addRocketTestSuites
     TestSuiteHelper.addBoomTestSuites
+    TestSuiteHelper.addArianeTestSuites
 
     // if hwacha parameter exists then generate its tests
     // TODO: find a more elegant way to do this. either through

generators/chipyard/src/main/scala/Subsystem.scala

@@ -22,24 +22,26 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.amba.axi4._
 
 import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams}
+import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
 
-
-trait HasBoomAndRocketTiles extends HasTiles
+trait HasChipyardTiles extends HasTiles
   with CanHavePeripheryPLIC
   with CanHavePeripheryCLINT
   with HasPeripheryDebug
 { this: BaseSubsystem =>
 
-  val module: HasBoomAndRocketTilesModuleImp
+  val module: HasChipyardTilesModuleImp
 
   protected val rocketTileParams = p(RocketTilesKey)
   protected val boomTileParams = p(BoomTilesKey)
+  protected val arianeTileParams = p(ArianeTilesKey)
 
   // crossing can either be per tile or global (aka only 1 crossing specified)
   private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
   private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
+  private val arianeCrossings = perTileOrGlobalSetting(p(ArianeCrossingKey), arianeTileParams.size)
 
-  val allTilesInfo = (rocketTileParams ++ boomTileParams) zip (rocketCrossings ++ boomCrossings)
+  val allTilesInfo = (rocketTileParams ++ boomTileParams ++ arianeTileParams) zip (rocketCrossings ++ boomCrossings ++ arianeCrossings)
 
   // Make a tile and wire its nodes into the system,
   // according to the specified type of clock crossing.
@@ -59,6 +61,10 @@ trait HasBoomAndRocketTiles extends HasTiles
           val t = LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
           (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
         }
+        case a: ArianeTileParams => {
+          val t = LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
+          (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
+        }
       }
       connectMasterPortsToSBus(tile, crossing)
       connectSlavePortsToCBus(tile, crossing)
@@ -79,14 +85,14 @@ trait HasBoomAndRocketTiles extends HasTiles
   }.toList
 }
 
-trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp
+trait HasChipyardTilesModuleImp extends HasTilesModuleImp
   with HasPeripheryDebugModuleImp
 {
-  val outer: HasBoomAndRocketTiles
+  val outer: HasChipyardTiles
 }
 
 class Subsystem(implicit p: Parameters) extends BaseSubsystem
-  with HasBoomAndRocketTiles
+  with HasChipyardTiles
 {
   override lazy val module = new SubsystemModuleImp(this)
 
@@ -95,7 +101,7 @@ class Subsystem(implicit p: Parameters) extends BaseSubsystem
 
 class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
   with HasResetVectorWire
-  with HasBoomAndRocketTilesModuleImp
+  with HasChipyardTilesModuleImp
 {
   tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
     wire.hartid := i.U

generators/chipyard/src/main/scala/TestSuites.scala

@@ -9,6 +9,7 @@ import freechips.rocketchip.util.{GeneratorApp}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
 
 import boom.common.{BoomTilesKey}
+import ariane.{ArianeTilesKey}
 
 /**
  * A set of pre-chosen regression tests
@@ -139,4 +140,44 @@ object TestSuiteHelper
       TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
     }
   }
+
+  /**
+  * Add Ariane tests (asm, bmark, regression)
+  */
+  def addArianeTestSuites(implicit p: Parameters) = {
+    val xlen = p(XLen)
+    p(ArianeTilesKey).find(_.hartId == 0).map { tileParams =>
+      val coreParams = tileParams.core
+      val vm = coreParams.useVM
+      val env = if (vm) List("p","v") else List("p")
+      coreParams.fpu foreach { case cfg =>
+        if (xlen == 32) {
+          TestGeneration.addSuites(env.map(rv32uf))
+          if (cfg.fLen >= 64)
+            TestGeneration.addSuites(env.map(rv32ud))
+        } else {
+          TestGeneration.addSuite(rv32udBenchmarks)
+          TestGeneration.addSuites(env.map(rv64uf))
+          if (cfg.fLen >= 64)
+            TestGeneration.addSuites(env.map(rv64ud))
+        }
+      }
+      if (coreParams.useAtomics) {
+        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+        else
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
+      }
+      if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      val (rvi, rvu) =
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        else            ((if (vm) rv32i else rv32pi), rv32u)
+
+      TestGeneration.addSuites(rvi.map(_("p")))
+      TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      TestGeneration.addSuite(benchmarks)
+      TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+    }
+  }
+
 }

generators/chipyard/src/main/scala/config/BoomConfigs.scala

@@ -6,7 +6,6 @@ import freechips.rocketchip.config.{Config}
 // BOOM Configs
 // ---------------------
 
-
 class SmallBoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
   new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
@@ -26,7 +25,6 @@ class SmallBoomConfig extends Config(
   new boom.common.WithNBoomCores(1) ++                           // single-core boom
   new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
 
-
 class MediumBoomConfig extends Config(
   new chipyard.iobinders.WithUARTAdapter ++
   new chipyard.iobinders.WithTieOffInterrupts ++

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -21,11 +21,12 @@ import midas.targetutils.{MemModelAnnotation}
 import firesim.bridges._
 import firesim.configs.MemModelKey
 import tracegen.HasTraceGenTilesModuleImp
+import ariane.ArianeTile
 
 import boom.common.{BoomTile}
 
 import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
-import chipyard.HasBoomAndRocketTilesModuleImp
+import chipyard.HasChipyardTilesModuleImp
 
 class WithSerialBridge extends OverrideIOBinder({
   (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq
@@ -67,7 +68,7 @@ class WithTraceGenBridge extends OverrideIOBinder({
 })
 
 class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
-  (c, r, s, target: HasBoomAndRocketTilesModuleImp) => {
+  (c, r, s, target: HasChipyardTilesModuleImp) => {
     target.outer.tiles.map {
       case r: RocketTile => {
         annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
@@ -84,6 +85,7 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
           case _ => Nil
         }
       }
+      case a: ArianeTile => Nil
     }
     Nil
   }

generators/firechip/src/main/scala/Generator.scala

@@ -26,6 +26,7 @@ trait HasTestSuites {
   def addTestSuites(targetName: String, params: Parameters) {
     TestSuiteHelper.addRocketTestSuites(params)
     TestSuiteHelper.addBoomTestSuites(params)
+    TestSuiteHelper.addArianeTestSuites(params)
     TestGeneration.addSuite(FastBlockdevTests)
     TestGeneration.addSuite(SlowBlockdevTests)
     if (!targetName.contains("NoNIC"))
@@ -61,7 +62,7 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike {
   override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   lazy val generatorArgs = GeneratorArgs(args)
   lazy val genDir = new File(names.targetDir)
-  // The only reason this is not generateFirrtl; generateAnno is that we need to use a different 
+  // The only reason this is not generateFirrtl; generateAnno is that we need to use a different
   // JsonProtocol to properly write out the annotations. Fix once the generated are unified
   elaborate
   generateTestSuiteMakefrags

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -19,6 +19,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import scala.math.{min, max}
 import tracegen.TraceGenKey
 import icenet._
+import ariane.ArianeTilesKey
 import testchipip.WithRingSystemBus
 
 import firesim.bridges._
@@ -76,6 +77,7 @@ class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
 // Enables tracing on all cores
 class WithTraceIO extends Config((site, here, up) => {
   case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+  case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
   case TracePortKey => Some(TracePortParams())
 })
 
@@ -165,3 +167,12 @@ class SupernodeFireSimRocketConfig extends Config(
   new WithNumNodes(4) ++
   new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8 GB
   new FireSimRocketConfig)
+
+//**********************************************************************************
+//* Ariane Configurations
+//*********************************************************************************/
+class FireSimArianeConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.ArianeConfig)