Rename top-level example package to chipyard

* FireChip now directly uses the Chipyard Top

generators/chipyard/src/main/scala/BoomConfigs.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import chisel3._
 

generators/chipyard/src/main/scala/ConfigMixins.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import chisel3._
 import chisel3.util.{log2Up}

generators/chipyard/src/main/scala/GCD.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import chisel3._
 import chisel3.util._

generators/chipyard/src/main/scala/Generator.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import scala.util.Try
 
@@ -8,8 +8,6 @@ import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.util.{GeneratorApp}
 import freechips.rocketchip.system.{TestGeneration}
 
-import utilities.{TestSuiteHelper}
-
 object Generator extends GeneratorApp {
   // add unique test suites
   override def addTestSuites {

generators/chipyard/src/main/scala/HeteroConfigs.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import chisel3._
 

generators/chipyard/src/main/scala/InitZero.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import chisel3._
 import chisel3.util._

generators/chipyard/src/main/scala/NodeTypes.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._

generators/chipyard/src/main/scala/RocketConfigs.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import chisel3._
 

generators/chipyard/src/main/scala/Subsystem.scala

@@ -3,7 +3,7 @@
 // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
 //------------------------------------------------------------------------------
 
-package utilities
+package chipyard
 
 import chisel3._
 import chisel3.internal.sourceinfo.{SourceInfo}

generators/chipyard/src/main/scala/System.scala

@@ -3,7 +3,7 @@
 // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
 //------------------------------------------------------------------------------
 
-package utilities
+package chipyard
 
 import chisel3._
 

generators/chipyard/src/main/scala/TestHarness.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import chisel3._
 import chisel3.experimental._

generators/chipyard/src/main/scala/TestSuites.scala

@@ -1,4 +1,4 @@
-package utilities
+package chipyard
 
 import scala.collection.mutable.{LinkedHashSet}
 

generators/chipyard/src/main/scala/Top.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import chisel3._
 
@@ -10,8 +10,6 @@ import freechips.rocketchip.util.DontTouch
 
 import testchipip._
 
-import utilities.{System, SystemModule}
-
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
 

generators/chipyard/src/main/scala/TopCakes.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import chisel3._
 

generators/firechip/src/main/scala/Generator.scala

@@ -20,7 +20,7 @@ import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGenerat
 
 import scala.util.Try
 
-import utilities.TestSuiteHelper
+import chipyard.TestSuiteHelper
 
 trait HasTestSuites {
   def addTestSuites(targetName: String, params: Parameters) {

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -114,6 +114,7 @@ class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache
 * determine which driver to build.
 *******************************************************************************/
 class FireSimRocketChipConfig extends Config(
+  new chipyard.WithNoGPIO ++
   new WithBootROM ++
   new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
   new WithExtMemSize(0x400000000L) ++ // 16GB
@@ -172,6 +173,7 @@ class FireSimRocketChipSha3L2PrintfConfig extends Config(
   new FireSimRocketChipConfig)
 
 class FireSimBoomConfig extends Config(
+  new chipyard.WithNoGPIO ++
   new WithBootROM ++
   new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
   new WithExtMemSize(0x400000000L) ++ // 16GB

generators/firechip/src/main/scala/TargetMixins.scala

@@ -51,7 +51,7 @@ trait HasTraceIOImp extends LazyModuleImp {
 }
 
 trait CanHaveMultiCycleRegfileImp {
-  val outer: utilities.HasBoomAndRocketTiles
+  val outer: chipyard.HasBoomAndRocketTiles
 
   outer.tiles.map {
     case r: RocketTile => {

generators/firechip/src/main/scala/Targets.scala

@@ -12,7 +12,6 @@ import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.amba.axi4.AXI4Bundle
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy.LazyModule
-import utilities.{Subsystem, SubsystemModuleImp}
 import icenet._
 import firesim.util.DefaultFireSimHarness
 import testchipip._
@@ -38,53 +37,20 @@ import FireSimValName._
 * determine which driver to build.
 *******************************************************************************/
 
-class FireSimDUT(implicit p: Parameters) extends Subsystem
-    with HasHierarchicalBusTopology
-    with CanHaveMasterAXI4MemPort
-    with HasPeripheryBootROM
-    with CanHavePeripherySerial
-    with HasPeripheryUART
-    with CanHavePeripheryIceNIC
-    with CanHavePeripheryBlockDevice
+class FireSimDUT(implicit p: Parameters) extends chipyard.Top
     with HasTraceIO
 {
   override lazy val module = new FireSimModuleImp(this)
 }
 
-class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l)
-    with HasRTCModuleImp
-    with CanHaveMasterAXI4MemPortModuleImp
-    with HasPeripheryBootROMModuleImp
-    with CanHavePeripherySerialModuleImp
-    with HasPeripheryUARTModuleImp
-    with HasPeripheryIceNICModuleImpValidOnly
-    with CanHavePeripheryBlockDeviceModuleImp
+class FireSimModuleImp[+L <: FireSimDUT](l: L) extends chipyard.TopModule(l)
     with HasTraceIOImp
     with CanHaveMultiCycleRegfileImp
 
 class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)
 
-class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem
-    with HasHierarchicalBusTopology
-    with CanHaveMasterAXI4MemPort
-    with HasPeripheryBootROM
-    with CanHavePeripherySerial
-    with HasPeripheryUART
-    with CanHavePeripheryBlockDevice
-    with HasTraceIO
-{
-  override lazy val module = new FireSimNoNICModuleImp(this)
-}
-
-class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModuleImp(l)
-    with HasRTCModuleImp
-    with CanHaveMasterAXI4MemPortModuleImp
-    with HasPeripheryBootROMModuleImp
-    with CanHavePeripherySerialModuleImp
-    with HasPeripheryUARTModuleImp
-    with CanHavePeripheryBlockDeviceModuleImp
-    with HasTraceIOImp
-    with CanHaveMultiCycleRegfileImp
+// Kept for legacy-reasons, this is equivalent to FireSimDUT
+class FireSimNoNICDUT(implicit p: Parameters) extends FireSimDUT
 
 class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT)
 
@@ -107,7 +73,7 @@ class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(()
 
 // Verilog blackbox integration demo
 class FireSimVerilogGCDDUT(implicit p: Parameters) extends FireSimDUT
-    with example.CanHavePeripheryGCD
+    with chipyard.CanHavePeripheryGCD
 {
   override lazy val module = new FireSimVerilogGCDModuleImp(this)
 }