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Many changes to begin the compilation with RC-1.3

Browse Source 
Cores now have an extra CoreParam, useSupervisor which was set to
the default false. Whether a core has supervisor mode is the union
of this and useVM which defaults true so not change was made by this
addition.

BusTopologies are now set with the Config system rather than a system
mixin and so all configs now include the config most similar to the
previous mixin
Testchipip was updated to be able to replace the systembus, in this
new config system, with a ring bus.

The L2 cache repo needed a similar update on how to find the buses.
It currently points to the ucb-bar fork

Treadle is bumped to its release branch
This commit is contained in:
Colin Schmidt
2020-05-05 14:57:54 -07:00
parent 63c46d89c1
commit 43f6083b69
14 changed files with 51 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
.gitmodules vendored
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@@ -33,7 +33,7 @@
url = https://github.com/firesim/icenet.git
[submodule "generators/block-inclusivecache-sifive"]
path = generators/sifive-cache
url = https://github.com/sifive/block-inclusivecache-sifive.git
url = https://github.com/ucb-bar/block-inclusivecache-sifive.git
[submodule "toolchains/riscv-tools/riscv-gnu-toolchain"]
path = toolchains/riscv-tools/riscv-gnu-toolchain
url = https://github.com/riscv/riscv-gnu-toolchain.git

2
generators/ariane

Submodule generators/ariane updated: f4ba64a624...1086f90223

2
generators/boom

Submodule generators/boom updated: 90911dde1b...79c0e5583c

1
generators/chipyard/src/main/scala/System.scala
View File

@@ -22,7 +22,6 @@ import freechips.rocketchip.util.{DontTouch}
* Base top with periphery devices and ports, and a BOOM + Rocket subsystem
*/
class System(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology
with HasAsyncExtInterrupts
with CanHaveMasterAXI4MemPort
with CanHaveMasterAXI4MMIOPort

2
generators/chipyard/src/main/scala/config/ArianeConfigs.scala
View File

@@ -22,6 +22,7 @@ class ArianeConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new ariane.WithNArianeCores(1) ++ // single Ariane core
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class dmiArianeConfig extends Config(
@@ -37,4 +38,5 @@ class dmiArianeConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new ariane.WithNArianeCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

8
generators/chipyard/src/main/scala/config/BoomConfigs.scala
View File

@@ -22,6 +22,7 @@ class SmallBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new boom.common.WithSmallBooms ++ // small boom config
new boom.common.WithNBoomCores(1) ++ // single-core boom
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class MediumBoomConfig extends Config(
@@ -40,6 +41,7 @@ class MediumBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithMediumBooms ++ // medium boom config
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class LargeBoomConfig extends Config(
@@ -58,6 +60,7 @@ class LargeBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithLargeBooms ++ // large boom config
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class MegaBoomConfig extends Config(
@@ -76,6 +79,7 @@ class MegaBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithMegaBooms ++ // mega boom config
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class DualSmallBoomConfig extends Config(
@@ -94,6 +98,7 @@ class DualSmallBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithSmallBooms ++
new boom.common.WithNBoomCores(2) ++ // 2 boom cores
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class SmallRV32BoomConfig extends Config(
@@ -114,6 +119,7 @@ class SmallRV32BoomConfig extends Config(
new boom.common.WithBoomRV32 ++ // rv32 (32bit)
new boom.common.WithSmallBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class HwachaLargeBoomConfig extends Config(
@@ -133,6 +139,7 @@ class HwachaLargeBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class LoopbackNICLargeBoomConfig extends Config(
@@ -153,5 +160,6 @@ class LoopbackNICLargeBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

7
generators/chipyard/src/main/scala/config/HeteroConfigs.scala
View File

@@ -24,6 +24,7 @@ class LargeBoomAndRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
// DOC include start: BoomAndRocketWithHwacha
@@ -46,6 +47,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: BoomAndRocketWithHwacha
@@ -67,6 +69,7 @@ class DualLargeBoomAndRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: DualBoomAndRocketOneHwacha
@@ -91,6 +94,7 @@ class LargeBoomAndHwachaRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: DualBoomAndRocketOneHwacha
@@ -115,6 +119,7 @@ class LargeBoomAndRV32RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
@@ -137,6 +142,7 @@ class DualLargeBoomAndDualRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: DualBoomAndRocket
@@ -159,5 +165,6 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

19
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -21,6 +21,7 @@ class RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class HwachaRocketConfig extends Config(
@@ -39,6 +40,7 @@ class HwachaRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: GemminiRocketConfig
@@ -58,6 +60,7 @@ class GemminiRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: GemminiRocketConfig
@@ -77,6 +80,7 @@ class RoccRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: JtagRocket
@@ -96,6 +100,7 @@ class jtagRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: JtagRocket
@@ -114,6 +119,7 @@ class dmiRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: DmiRocket
@@ -134,6 +140,7 @@ class GCDTLRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: GCDTLRocketConfig
@@ -154,6 +161,7 @@ class GCDAXI4BlackBoxRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: GCDAXI4BlackBoxRocketConfig
@@ -174,6 +182,7 @@ class SimBlockDeviceRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class BlockDeviceModelRocketConfig extends Config(
@@ -193,6 +202,7 @@ class BlockDeviceModelRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: GPIORocketConfig
@@ -213,6 +223,7 @@ class GPIORocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: GPIORocketConfig
@@ -231,6 +242,7 @@ class QuadRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles)
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class RV32RocketConfig extends Config(
@@ -248,6 +260,7 @@ class RV32RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class GB1MemoryRocketConfig extends Config(
@@ -266,6 +279,7 @@ class GB1MemoryRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: Sha3Rocket
@@ -285,6 +299,7 @@ class Sha3RocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: Sha3Rocket
@@ -305,6 +320,7 @@ class InitZeroRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: InitZeroRocketConfig
@@ -325,6 +341,7 @@ class LoopbackNICRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: scratchpadrocket
@@ -344,6 +361,7 @@ class ScratchpadRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: scratchpadrocket
@@ -364,5 +382,6 @@ class RingSystemBusRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include end: RingSystemBusRocket

5
generators/chipyard/src/main/scala/config/TracegenConfigs.scala
View File

@@ -8,6 +8,7 @@ class TraceGenConfig extends Config(
new chipyard.iobinders.WithTraceGenSuccessBinder ++
new chipyard.config.WithTracegenSystem ++
new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class NonBlockingTraceGenConfig extends Config(
@@ -15,6 +16,7 @@ class NonBlockingTraceGenConfig extends Config(
new chipyard.iobinders.WithTraceGenSuccessBinder ++
new chipyard.config.WithTracegenSystem ++
new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class BoomTraceGenConfig extends Config(
@@ -23,6 +25,7 @@ class BoomTraceGenConfig extends Config(
new chipyard.config.WithTracegenSystem ++
new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class NonBlockingTraceGenL2Config extends Config(
@@ -31,6 +34,7 @@ class NonBlockingTraceGenL2Config extends Config(
new chipyard.config.WithTracegenSystem ++
new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class NonBlockingTraceGenL2RingConfig extends Config(
@@ -40,4 +44,5 @@ class NonBlockingTraceGenL2RingConfig extends Config(
new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
new testchipip.WithRingSystemBus ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)

4
generators/chipyard/src/main/scala/config/TutorialConfigs.scala
View File

@@ -50,6 +50,7 @@ class TutorialStarterConfig extends Config(
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
// BaseConfig configures "bare" rocketchip system
new freechips.rocketchip.system.BaseConfig
)
@@ -79,6 +80,7 @@ class TutorialMMIOConfig extends Config(
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig
)
@@ -104,6 +106,7 @@ class TutorialSha3Config extends Config(
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig
)
@@ -130,5 +133,6 @@ class TutorialSha3BlackBoxConfig extends Config(
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig
)

2
generators/sifive-cache

Submodule generators/sifive-cache updated: d3d95ece5a...9ac1a5242d

2
generators/testchipip

Submodule generators/testchipip updated: cec2c0b6d6...8fbd4f43b6

1
generators/tracegen/src/main/scala/System.scala
View File

@@ -41,7 +41,6 @@ trait HasTraceGenTilesModuleImp extends LazyModuleImp {
class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
with HasTraceGenTiles
with HasHierarchicalBusTopology
with CanHaveMasterAXI4MemPort {
override lazy val module = new TraceGenSystemModuleImp(this)
}

2
tools/treadle

Submodule tools/treadle updated: a03b969af1...6ca4fec611