Increase verilator reset length

This commit is contained in:
Colin Schmidt
2020-05-06 18:39:42 -07:00
parent 006ecd2b7c
commit 3c18880064

View File

@@ -283,7 +283,7 @@ done_processing:
bool dump;
// reset for several cycles to handle pipelined reset
for (int i = 0; i < 10; i++) {
for (int i = 0; i < 100; i++) {
tile->reset = 1;
tile->clock = 0;
tile->eval();