Merge remote-tracking branch 'origin/dev' into firesim-multiclock

[ci skip]

generators/chipyard/src/main/scala/ArianeConfigs.scala

@@ -0,0 +1,42 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+// ---------------------
+// Ariane Configs
+// ---------------------
+
+class ArianeConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
+  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
+  new chipyard.iobinders.WithSimAXIMem ++                        // drive the master AXI4 memory with a SimAXIMem
+  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
+  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
+  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
+  new chipyard.config.WithNoGPIO ++                              // no top-level GPIO pins (overrides default set in sifive-blocks)
+  new chipyard.config.WithBootROM ++                             // use default bootrom
+  new chipyard.config.WithUART ++                                // add a UART
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
+  new ariane.WithNArianeCores(1) ++                              // single Ariane core
+  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
+
+class dmiArianeConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithSimAXIMem ++
+  new chipyard.iobinders.WithTiedOffSerial ++
+  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new ariane.WithNArianeCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -0,0 +1,152 @@
+package chipyard.config
+
+import chisel3._
+import chisel3.util.{log2Up}
+
+import freechips.rocketchip.config.{Field, Parameters, Config}
+import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, CacheBlockBytes}
+import freechips.rocketchip.diplomacy.{LazyModule, ValName}
+import freechips.rocketchip.devices.tilelink.BootROMParams
+import freechips.rocketchip.devices.debug.{Debug}
+import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC, RocketTileParams, MaxHartIdBits}
+import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
+import freechips.rocketchip.util.{AsyncResetReg}
+
+import boom.common.{BoomTilesKey}
+
+import testchipip._
+
+import hwacha.{Hwacha}
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.uart._
+
+import chipyard.{BuildTop}
+
+/**
+ * TODO: Why do we need this?
+ */
+object ConfigValName {
+  implicit val valName = ValName("TestHarness")
+}
+import ConfigValName._
+
+// -----------------------
+// Common Config Fragments
+// -----------------------
+
+class WithBootROM extends Config((site, here, up) => {
+  case BootROMParams => BootROMParams(
+    contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
+})
+
+// DOC include start: gpio config fragment
+class WithGPIO extends Config((site, here, up) => {
+  case PeripheryGPIOKey => Seq(
+    GPIOParams(address = 0x10012000, width = 4, includeIOF = false))
+})
+// DOC include end: gpio config fragment
+
+class WithUART extends Config((site, here, up) => {
+  case PeripheryUARTKey => Seq(
+    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256))
+})
+
+class WithNoGPIO extends Config((site, here, up) => {
+  case PeripheryGPIOKey => Seq()
+})
+
+class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
+    core = tile.core.copy(nL2TLBEntries = entries)
+  ))
+  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(
+    core = tile.core.copy(nL2TLBEntries = entries)
+  ))
+})
+
+class WithTracegenTop extends Config((site, here, up) => {
+  case BuildTop => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module)
+})
+
+
+class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) =>
+    r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length))
+  }
+  case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) =>
+    b.copy(hartId = i + (if(rocketFirst) up(RocketTilesKey, site).length else 0))
+  }
+  case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size)
+})
+
+
+
+// ------------------
+// Multi-RoCC Support
+// ------------------
+
+/**
+ * Map from a hartId to a particular RoCC accelerator
+ */
+case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]])
+
+/**
+ * Config fragment to enable different RoCCs based on the hartId
+ */
+class WithMultiRoCC extends Config((site, here, up) => {
+  case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil)
+})
+
+/**
+ * Config fragment to add Hwachas to cores based on hart
+ *
+ * For ex:
+ *   Core 0, 1, 2, 3 have been defined earlier
+ *     with hartIds of 0, 1, 2, 3 respectively
+ *   And you call WithMultiRoCCHwacha(0,1)
+ *   Then Core 0 and 1 will get a Hwacha
+ *
+ * @param harts harts to specify which will get a Hwacha
+ */
+class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
+  case MultiRoCCKey => {
+    require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1))
+    up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
+      (i -> Seq((p: Parameters) => {
+        LazyModule(new Hwacha()(p)).suggestName("hwacha")
+      }))
+    }
+  }
+})
+
+
+/**
+ * Config fragment to add a small Rocket core to the system as a "control" core.
+ * Used as an example of a PMU core.
+ */
+class WithControlCore extends Config((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey, site) :+
+    RocketTileParams(
+      core = RocketCoreParams(
+        useVM = false,
+        fpu = None,
+        mulDiv = Some(MulDivParams(mulUnroll = 8))),
+      btb = None,
+      dcache = Some(DCacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBEntries = 4,
+        nMSHRs = 0,
+        blockBytes = site(CacheBlockBytes))),
+      icache = Some(ICacheParams(
+        rowBits = site(SystemBusKey).beatBits,
+        nSets = 64,
+        nWays = 1,
+        nTLBEntries = 4,
+        blockBytes = site(CacheBlockBytes))),
+      hartId = up(RocketTilesKey, site).size + up(BoomTilesKey, site).size
+    )
+  case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
+})

generators/chipyard/src/main/scala/Generator.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard
 
 import scala.util.Try
 
@@ -8,14 +8,13 @@ import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.util.{GeneratorApp}
 import freechips.rocketchip.system.{TestGeneration}
 
-import utilities.{TestSuiteHelper}
-
 object Generator extends GeneratorApp {
   // add unique test suites
   override def addTestSuites {
     implicit val p: Parameters = params
     TestSuiteHelper.addRocketTestSuites
     TestSuiteHelper.addBoomTestSuites
+    TestSuiteHelper.addArianeTestSuites
 
     // if hwacha parameter exists then generate its tests
     // TODO: find a more elegant way to do this. either through

generators/chipyard/src/main/scala/IOBinders.scala

@@ -0,0 +1,186 @@
+package chipyard.iobinders
+
+import chisel3._
+
+import freechips.rocketchip.config.{Field, Config, Parameters}
+import freechips.rocketchip.diplomacy.{LazyModule}
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.system._
+import freechips.rocketchip.util._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.uart._
+
+import testchipip._
+import icenet._
+import tracegen.{HasTraceGenTilesModuleImp}
+
+import scala.reflect.{ClassTag}
+
+// System for instantiating binders based
+// on the scala type of the Target (_not_ its IO). This avoids needing to
+// duplicate harnesses (essentially test harnesses) for each target.
+
+// IOBinders is map between string representations of traits to the desired
+// IO connection behavior for tops matching that trait. We use strings to enable
+// composition and overriding of IOBinders, much like how normal Keys in the config
+// system are used/ At elaboration, the testharness traverses this set of functions,
+// and functions which match the type of the Top are evaluated.
+
+// You can add your own binder by adding a new (key, fn) pair, typically by using
+// the OverrideIOBinder or ComposeIOBinder macros
+
+// DOC include start: IOBinders
+case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]](
+  Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]().withDefaultValue((c: Clock, r: Bool, s: Bool, t: Any) => Nil)
+)
+
+// This macro overrides previous matches on some Top mixin. This is useful for
+// binders which drive IO, since those typically cannot be composed
+class OverrideIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
+  case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString ->
+      ((clock: Clock, reset: Bool, success: Bool, t: Any) => {
+        t match {
+          case top: T => fn(clock, reset, success, top)
+          case _ => Nil
+        }
+      })
+  )
+})
+
+// This macro composes with previous matches on some Top mixin. This is useful for
+// annotation-like binders, since those can typically be composed
+class ComposeIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
+  case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString ->
+      ((clock: Clock, reset: Bool, success: Bool, t: Any) => {
+        t match {
+          case top: T => (up(IOBinders, site)(tag.runtimeClass.toString)(clock, reset, success, top)
+            ++ fn(clock, reset, success, top))
+          case _ => Nil
+        }
+      })
+  )
+})
+
+// DOC include end: IOBinders
+
+class WithGPIOTiedOff extends OverrideIOBinder({
+  (c, r, s, top: HasPeripheryGPIOModuleImp) => top.gpio.map(gpio => gpio.pins.map(p => p.i.ival := false.B)); Nil
+})
+
+class WithSimBlockDevice extends OverrideIOBinder({
+  (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectSimBlockDevice(c, r); Nil
+})
+
+class WithBlockDeviceModel extends OverrideIOBinder({
+  (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectBlockDeviceModel(); Nil
+})
+
+class WithLoopbackNIC extends OverrideIOBinder({
+  (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectNicLoopback(); Nil
+})
+
+class WithSimNIC extends OverrideIOBinder({
+  (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectSimNetwork(c, r); Nil
+})
+
+class WithUARTAdapter extends OverrideIOBinder({
+  (c, r, s, top: HasPeripheryUARTModuleImp) => {
+    val defaultBaudRate = 115200 // matches sifive-blocks uart baudrate
+    top.uart.zipWithIndex.foreach{ case (dut_io, i) =>
+      val uart_sim = Module(new UARTAdapter(i, defaultBaudRate)(top.p))
+      uart_sim.io.uart.txd := dut_io.txd
+      dut_io.rxd := uart_sim.io.uart.rxd
+    }
+    Nil
+  }
+})
+
+// DOC include start: WithSimAXIMem
+class WithSimAXIMem extends OverrideIOBinder({
+  (c, r, s, top: CanHaveMasterAXI4MemPortModuleImp) => top.connectSimAXIMem(); Nil
+})
+// DOC include end: WithSimAXIMem
+
+class WithBlackBoxSimMem extends OverrideIOBinder({
+  (clock, reset, _, top: CanHaveMasterAXI4MemPortModuleImp) => {
+    (top.mem_axi4 zip top.outer.memAXI4Node).foreach { case (io, node) =>
+      val memSize = top.p(ExtMem).get.master.size
+      val lineSize = top.p(CacheBlockBytes)
+      (io zip node.in).foreach { case (axi4, (_, edge)) =>
+        val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle))
+        mem.io.axi <> axi4
+        mem.io.clock := clock
+        mem.io.reset := reset
+      }
+    }; Nil
+  }
+})
+
+class WithSimAXIMMIO extends OverrideIOBinder({
+  (c, r, s, top: CanHaveMasterAXI4MMIOPortModuleImp) => top.connectSimAXIMMIO(); Nil
+})
+
+class WithDontTouchPorts extends OverrideIOBinder({
+  (c, r, s, top: DontTouch) => top.dontTouchPorts(); Nil
+})
+
+class WithTieOffInterrupts extends OverrideIOBinder({
+  (c, r, s, top: HasExtInterruptsBundle) => top.tieOffInterrupts(); Nil
+})
+
+class WithTieOffL2FBusAXI extends OverrideIOBinder({
+  (c, r, s, top: CanHaveSlaveAXI4PortModuleImp) => {
+    top.l2_frontend_bus_axi4.foreach(axi => {
+      axi.tieoff()
+      experimental.DataMirror.directionOf(axi.ar.ready) match {
+        case ActualDirection.Input =>
+          axi.r.bits := DontCare
+          axi.b.bits := DontCare
+        case ActualDirection.Output =>
+          axi.aw.bits := DontCare
+          axi.ar.bits := DontCare
+          axi.w.bits := DontCare
+      }
+    })
+    Nil
+  }
+})
+
+class WithTiedOffDebug extends OverrideIOBinder({
+  (c, r, s, top: HasPeripheryDebugModuleImp) => {
+    Debug.tieoffDebug(top.debug, top.psd)
+    // tieoffDebug doesn't actually tie everything off :/
+    top.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }))
+    Nil
+  }
+})
+
+class WithSimSerial extends OverrideIOBinder({
+  (c, r, s, top: CanHavePeripherySerialModuleImp) => {
+    val ser_success = top.connectSimSerial()
+    when (ser_success) { s := true.B }
+    Nil
+  }
+})
+
+class WithTiedOffSerial extends OverrideIOBinder({
+  (c, r, s, top: CanHavePeripherySerialModuleImp) => top.tieoffSerial(); Nil
+})
+
+
+class WithSimDebug extends OverrideIOBinder({
+  (c, r, s, top: HasPeripheryDebugModuleImp) => {
+    val dtm_success = Wire(Bool())
+    top.reset := r | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B)
+    Debug.connectDebug(top.debug, top.psd, c, r, dtm_success)(top.p)
+    when (dtm_success) { s := true.B }
+    Nil
+  }
+})
+
+
+class WithTraceGenSuccessBinder extends OverrideIOBinder({
+  (c, r, s, top: HasTraceGenTilesModuleImp) => when (top.success) { s := true.B };  Nil
+})

generators/chipyard/src/main/scala/Subsystem.scala

@@ -3,7 +3,7 @@
 // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
 //------------------------------------------------------------------------------
 
-package utilities
+package chipyard
 
 import chisel3._
 import chisel3.internal.sourceinfo.{SourceInfo}
@@ -22,24 +22,26 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.amba.axi4._
 
 import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams}
+import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
 
-
-trait HasBoomAndRocketTiles extends HasTiles
+trait HasChipyardTiles extends HasTiles
   with CanHavePeripheryPLIC
   with CanHavePeripheryCLINT
   with HasPeripheryDebug
 { this: BaseSubsystem =>
 
-  val module: HasBoomAndRocketTilesModuleImp
+  val module: HasChipyardTilesModuleImp
 
   protected val rocketTileParams = p(RocketTilesKey)
   protected val boomTileParams = p(BoomTilesKey)
+  protected val arianeTileParams = p(ArianeTilesKey)
 
   // crossing can either be per tile or global (aka only 1 crossing specified)
   private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
   private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
+  private val arianeCrossings = perTileOrGlobalSetting(p(ArianeCrossingKey), arianeTileParams.size)
 
-  val allTilesInfo = (rocketTileParams ++ boomTileParams) zip (rocketCrossings ++ boomCrossings)
+  val allTilesInfo = (rocketTileParams ++ boomTileParams ++ arianeTileParams) zip (rocketCrossings ++ boomCrossings ++ arianeCrossings)
 
   // Make a tile and wire its nodes into the system,
   // according to the specified type of clock crossing.
@@ -59,6 +61,10 @@ trait HasBoomAndRocketTiles extends HasTiles
           val t = LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
           (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
         }
+        case a: ArianeTileParams => {
+          val t = LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
+          (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
+        }
       }
       connectMasterPortsToSBus(tile, crossing)
       connectSlavePortsToCBus(tile, crossing)
@@ -79,14 +85,14 @@ trait HasBoomAndRocketTiles extends HasTiles
   }.toList
 }
 
-trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp
+trait HasChipyardTilesModuleImp extends HasTilesModuleImp
   with HasPeripheryDebugModuleImp
 {
-  val outer: HasBoomAndRocketTiles
+  val outer: HasChipyardTiles
 }
 
 class Subsystem(implicit p: Parameters) extends BaseSubsystem
-  with HasBoomAndRocketTiles
+  with HasChipyardTiles
 {
   override lazy val module = new SubsystemModuleImp(this)
 
@@ -95,7 +101,7 @@ class Subsystem(implicit p: Parameters) extends BaseSubsystem
 
 class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
   with HasResetVectorWire
-  with HasBoomAndRocketTilesModuleImp
+  with HasChipyardTilesModuleImp
 {
   tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
     wire.hartid := i.U

generators/chipyard/src/main/scala/System.scala

@@ -3,7 +3,7 @@
 // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
 //------------------------------------------------------------------------------
 
-package utilities
+package chipyard
 
 import chisel3._
 

generators/chipyard/src/main/scala/TestHarness.scala

@@ -0,0 +1,30 @@
+package chipyard
+
+import chisel3._
+import chisel3.experimental._
+
+import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}
+
+import freechips.rocketchip.diplomacy.LazyModule
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.util.GeneratorApp
+import freechips.rocketchip.devices.debug.{Debug}
+
+import chipyard.config.ConfigValName._
+import chipyard.iobinders.{IOBinders}
+
+// -------------------------------
+// BOOM and/or Rocket Test Harness
+// -------------------------------
+
+case object BuildTop extends Field[Parameters => Any]((p: Parameters) => Module(LazyModule(new Top()(p)).suggestName("top").module))
+
+class TestHarness(implicit val p: Parameters) extends Module {
+  val io = IO(new Bundle {
+    val success = Output(Bool())
+  })
+
+  val dut = p(BuildTop)(p)
+  io.success := false.B
+  p(IOBinders).values.map(fn => fn(clock, reset.asBool, io.success, dut))
+}

generators/chipyard/src/main/scala/TestSuites.scala

@@ -1,4 +1,4 @@
-package utilities
+package chipyard
 
 import scala.collection.mutable.{LinkedHashSet}
 
@@ -9,6 +9,7 @@ import freechips.rocketchip.util.{GeneratorApp}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
 
 import boom.common.{BoomTilesKey}
+import ariane.{ArianeTilesKey}
 
 /**
  * A set of pre-chosen regression tests
@@ -139,4 +140,44 @@ object TestSuiteHelper
       TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
     }
   }
+
+  /**
+  * Add Ariane tests (asm, bmark, regression)
+  */
+  def addArianeTestSuites(implicit p: Parameters) = {
+    val xlen = p(XLen)
+    p(ArianeTilesKey).find(_.hartId == 0).map { tileParams =>
+      val coreParams = tileParams.core
+      val vm = coreParams.useVM
+      val env = if (vm) List("p","v") else List("p")
+      coreParams.fpu foreach { case cfg =>
+        if (xlen == 32) {
+          TestGeneration.addSuites(env.map(rv32uf))
+          if (cfg.fLen >= 64)
+            TestGeneration.addSuites(env.map(rv32ud))
+        } else {
+          TestGeneration.addSuite(rv32udBenchmarks)
+          TestGeneration.addSuites(env.map(rv64uf))
+          if (cfg.fLen >= 64)
+            TestGeneration.addSuites(env.map(rv64ud))
+        }
+      }
+      if (coreParams.useAtomics) {
+        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+        else
+          TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
+      }
+      if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      val (rvi, rvu) =
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        else            ((if (vm) rv32i else rv32pi), rv32u)
+
+      TestGeneration.addSuites(rvi.map(_("p")))
+      TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      TestGeneration.addSuite(benchmarks)
+      TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+    }
+  }
+
 }

generators/chipyard/src/main/scala/Top.scala

@@ -0,0 +1,38 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.system._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.devices.tilelink._
+
+// ------------------------------------
+// BOOM and/or Rocket Top Level Systems
+// ------------------------------------
+
+// DOC include start: Top
+class Top(implicit p: Parameters) extends System
+  with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
+  with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
+  with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
+  with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
+  with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
+  with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
+  with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
+  with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
+  with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
+{
+  override lazy val module = new TopModule(this)
+}
+
+class TopModule[+L <: Top](l: L) extends SystemModule(l)
+  with testchipip.CanHaveTraceIOModuleImp
+  with testchipip.CanHavePeripheryBlockDeviceModuleImp
+  with testchipip.CanHavePeripherySerialModuleImp
+  with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
+  with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
+  with icenet.CanHavePeripheryIceNICModuleImp
+  with chipyard.example.CanHavePeripheryGCDModuleImp
+  with freechips.rocketchip.util.DontTouch
+// DOC include end: Top

generators/chipyard/src/main/scala/config/BoomConfigs.scala

@@ -0,0 +1,165 @@
+package chipyard
+
+import freechips.rocketchip.config.{Config}
+
+// ---------------------
+// BOOM Configs
+// ---------------------
+
+class SmallBoomConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
+  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
+  new chipyard.iobinders.WithBlackBoxSimMem ++                   // drive the master AXI4 memory with a SimAXIMem
+  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
+  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
+  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
+  new chipyard.config.WithNoGPIO ++                              // no top-level GPIO pins (overrides default set in sifive-blocks)
+  new chipyard.config.WithBootROM ++                             // use default bootrom
+  new chipyard.config.WithUART ++                                // add a UART
+  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
+  new boom.common.WithSmallBooms ++                              // small boom config
+  new boom.common.WithNBoomCores(1) ++                           // single-core boom
+  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
+
+class MediumBoomConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new boom.common.WithMediumBooms ++                              // medium boom config
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class LargeBoomConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new boom.common.WithLargeBooms ++                              // large boom config
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class MegaBoomConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new boom.common.WithMegaBooms ++                              // mega boom config
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class DualSmallBoomConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new boom.common.WithSmallBooms ++
+  new boom.common.WithNBoomCores(2) ++                         // 2 boom cores
+  new freechips.rocketchip.system.BaseConfig)
+
+class SmallRV32BoomConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new boom.common.WithoutBoomFPU ++                        // no fp
+  new boom.common.WithBoomRV32 ++                          // rv32 (32bit)
+  new boom.common.WithSmallBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class HwachaLargeBoomConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new hwacha.DefaultHwachaConfig ++                         // use Hwacha vector accelerator
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class LoopbackNICLargeBoomConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new chipyard.iobinders.WithLoopbackNIC ++                        // drive NIC IOs with loopback
+  new testchipip.WithTSI ++
+  new icenet.WithIceNIC ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+

generators/chipyard/src/main/scala/config/HeteroConfigs.scala

@@ -0,0 +1,170 @@
+package chipyard
+
+import freechips.rocketchip.config.{Config}
+
+// ---------------------
+// Heterogenous Configs
+// ---------------------
+
+class LargeBoomAndRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
+  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
+  new chipyard.iobinders.WithBlackBoxSimMem ++                   // drive the master AXI4 memory with a SimAXIMem
+  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
+  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
+  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
+  new chipyard.config.WithNoGPIO ++                              // no top-level GPIO pins (overrides default set in sifive-blocks)
+  new chipyard.config.WithBootROM ++                             // use default bootrom
+  new chipyard.config.WithUART ++                                // add a UART
+  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
+  new chipyard.config.WithRenumberHarts ++                       // avoid hartid overlap
+  new boom.common.WithLargeBooms ++                              // 3-wide boom
+  new boom.common.WithNBoomCores(1) ++                           // single-core boom
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
+
+// DOC include start: BoomAndRocketWithHwacha
+class HwachaLargeBoomAndHwachaRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new hwacha.DefaultHwachaConfig ++                      // add hwacha to all harts
+  new chipyard.config.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: BoomAndRocketWithHwacha
+
+class DualLargeBoomAndRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new chipyard.config.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(2) ++                       // 2 boom cores
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+// DOC include start: DualBoomAndRocketOneHwacha
+
+class LargeBoomAndHwachaRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
+  new chipyard.config.WithMultiRoCCHwacha(1) ++                         // put hwacha on hart-2 (rocket)
+  new chipyard.config.WithL2TLBs(1024) ++
+  new chipyard.config.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: DualBoomAndRocketOneHwacha
+
+
+
+class LargeBoomAndRV32RocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new chipyard.config.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithRV32 ++           // set RocketTiles to be 32-bit
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+
+// DOC include start: DualBoomAndRocket
+class DualLargeBoomAndDualRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new chipyard.config.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(2) ++                     // 2 boom cores
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(2) ++   // 2 rocket cores
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: DualBoomAndRocket
+
+class LargeBoomAndRocketWithControlCoreConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithControlCore ++  // add small control core to last hartid
+  new chipyard.config.WithL2TLBs(1024) ++
+  new chipyard.config.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -0,0 +1,384 @@
+package chipyard
+
+import freechips.rocketchip.config.{Config}
+
+// --------------
+// Rocket Configs
+// --------------
+
+class RocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
+  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
+  new chipyard.iobinders.WithBlackBoxSimMem ++                   // drive the master AXI4 memory with a SimAXIMem
+  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
+  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
+  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
+  new chipyard.config.WithNoGPIO ++                              // no top-level GPIO pins (overrides default set in sifive-blocks)
+  new chipyard.config.WithBootROM ++                             // use default bootrom
+  new chipyard.config.WithUART ++                                // add a UART
+  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
+
+class HwachaRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new hwacha.DefaultHwachaConfig ++                        // use Hwacha vector accelerator
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+// DOC include start: GemminiRocketConfig
+class GemminiRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new gemmini.DefaultGemminiConfig ++                        // use Gemmini systolic array GEMM accelerator
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: GemminiRocketConfig
+
+class RoccRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithRoccExample ++    // use example RoCC-based accelerator
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+// DOC include start: JtagRocket
+class jtagRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithSimDebug ++    // add SimJtag and SimSerial, use both to drive sim
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithJtagDTM ++        // sets DTM communication interface to JTAG
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: JtagRocket
+
+// DOC include start: DmiRocket
+class dmiRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffSerial ++
+  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: DmiRocket
+
+// DOC include start: GCDTLRocketConfig
+class GCDTLRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++          // Use GCD Chisel, connect Tilelink
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: GCDTLRocketConfig
+
+// DOC include start: GCDAXI4BlackBoxRocketConfig
+class GCDAXI4BlackBoxRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++          // Use GCD blackboxed verilog, connect by AXI4->Tilelink
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: GCDAXI4BlackBoxRocketConfig
+
+class SimBlockDeviceRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new chipyard.iobinders.WithSimBlockDevice ++             // drive block-device IOs with SimBlockDevice
+  new testchipip.WithTSI ++
+  new testchipip.WithBlockDevice ++                        // add block-device module to peripherybus
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class BlockDeviceModelRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new chipyard.iobinders.WithBlockDeviceModel ++           // drive block-device IOs with a BlockDeviceModel
+  new testchipip.WithTSI ++
+  new testchipip.WithBlockDevice ++                        // add block-device module to periphery bus
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+// DOC include start: GPIORocketConfig
+class GPIORocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new chipyard.iobinders.WithGPIOTiedOff ++                // tie off GPIO inputs into the top
+  new testchipip.WithTSI ++
+  new chipyard.config.WithGPIO ++                          // add GPIOs to the peripherybus
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: GPIORocketConfig
+
+class QuadRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(4) ++   // quad-core (4 RocketTiles)
+  new freechips.rocketchip.system.BaseConfig)
+
+class RV32RocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithRV32 ++           // set RocketTiles to be 32-bit
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class GB1MemoryRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+// DOC include start: Sha3Rocket
+class Sha3RocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: Sha3Rocket
+
+// DOC include start: InitZeroRocketConfig
+class InitZeroRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++                // add InitZero
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: InitZeroRocketConfig
+
+class LoopbackNICRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new chipyard.iobinders.WithLoopbackNIC ++                        // drive NIC IOs with loopback
+  new testchipip.WithTSI ++
+  new icenet.WithIceNIC ++                                         // add an IceNIC
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+// DOC include start: scratchpadrocket
+class ScratchpadRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new testchipip.WithBackingScratchpad ++              // add backing scratchpad
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMemPort ++       // remove offchip mem port
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: scratchpadrocket
+
+class RingSystemBusRocketConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new testchipip.WithRingSystemBus ++ // Ring-topology system bus
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)

generators/chipyard/src/main/scala/config/TracegenConfigs.scala

@@ -0,0 +1,43 @@
+package chipyard
+
+import freechips.rocketchip.config.{Config}
+import freechips.rocketchip.rocket.{DCacheParams}
+
+class TraceGenConfig extends Config(
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTraceGenSuccessBinder ++
+  new chipyard.config.WithTracegenTop ++
+  new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class NonBlockingTraceGenConfig extends Config(
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTraceGenSuccessBinder ++
+  new chipyard.config.WithTracegenTop ++
+  new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class BoomTraceGenConfig extends Config(
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTraceGenSuccessBinder ++
+  new chipyard.config.WithTracegenTop ++
+  new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class NonBlockingTraceGenL2Config extends Config(
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTraceGenSuccessBinder ++
+  new chipyard.config.WithTracegenTop ++
+  new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class NonBlockingTraceGenL2RingConfig extends Config(
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTraceGenSuccessBinder ++
+  new chipyard.config.WithTracegenTop ++
+  new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
+  new testchipip.WithRingSystemBus ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.system.BaseConfig)

generators/chipyard/src/main/scala/config/TutorialConfigs.scala

@@ -0,0 +1,138 @@
+package chipyard
+
+import freechips.rocketchip.config.{Config}
+
+// This file is designed to accompany a live tutorial, with slides.
+// For each of 4 phases, participants will customize and build a
+// small demonstration config.
+
+// This file is designed to be used after running chipyard/scripts/tutorial-setup.sh,
+// which removes the SHA3 accelerator RTL, and provides participants
+// the experience of integrating external RTL.
+
+// This file was originally developed for the cancelled ASPLOS-2020
+// Chipyard tutorial. While the configs here work, the corresponding
+// slideware has not yet been created
+
+// NOTE: Configs should be read bottom-up, since they are applied bottom-up
+
+// Tutorial Phase 1: Configure the cores, caches
+class TutorialStarterConfig extends Config(
+  // IOBinders specify how to connect to IOs in our TestHarness
+  // These config fragments do not affect
+  new chipyard.iobinders.WithUARTAdapter ++       // Connect a SimUART adapter to display UART on stdout
+  new chipyard.iobinders.WithBlackBoxSimMem ++    // Connect simulated external memory
+  new chipyard.iobinders.WithTieOffInterrupts ++  // Do not simulate external interrupts
+  new chipyard.iobinders.WithTiedOffDebug ++      // Disconnect the debug module, since we use TSI for bring-up
+  new chipyard.iobinders.WithSimSerial ++         // Connect external SimSerial widget to drive TSI
+
+  // Config fragments below this line affect hardware generation
+  // of the Top
+  new testchipip.WithTSI ++                  // Add a TSI (Test Serial Interface)  widget to bring-up the core
+  new chipyard.config.WithNoGPIO ++          // Disable GPIOs.
+  new chipyard.config.WithBootROM ++         // Use the Chipyard BootROM
+  new chipyard.config.WithRenumberHarts ++   // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op
+  new chipyard.config.WithUART ++            // Add a UART
+
+  // CUSTOMIZE THE CORE
+  // Uncomment out one (or multiple) of the lines below, and choose
+  // how many cores you want.
+  // new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores
+  // new boom.common.WithSmallBooms ++                      // Specify all BOOM cores should be Small-sized (NOTE: other options are Medium/Large/Mega)
+  // new boom.common.WithNBoomCores(1) ++                   // Specify we want some number of BOOM cores
+
+  // CUSTOMIZE the L2
+  // Uncomment this line, and specify a size if you want to have a L2
+  // new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks=1, nWays=4, capacityKB=128) ++
+
+  // For simpler designs, we want to minimize IOs on
+  // our Top. These config fragments remove unnecessary
+  // ports
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  // BaseConfig configures "bare" rocketchip system
+  new freechips.rocketchip.system.BaseConfig
+)
+
+
+// Tutorial Phase 2: Integrate a TileLink or AXI4 MMIO device
+class TutorialMMIOConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithRenumberHarts ++
+  new chipyard.config.WithUART ++
+
+  // Attach either a TileLink or AXI4 version of GCD
+  // Uncomment one of the below lines
+  // new chipyard.example.WithGCD(useAXI4=false) ++ // Use TileLink version
+  // new chipyard.example.WithGCD(useAXI4=true) ++  // Use AXI4 version
+
+  // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.system.BaseConfig
+)
+
+// Tutorial Phase 3: Integrate a SHA3 RoCC accelerator
+class TutorialSha3Config extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithRenumberHarts ++
+  new chipyard.config.WithUART ++
+
+  // Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo
+  // new sha3.WithSha3Accel ++
+
+  // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.system.BaseConfig
+)
+
+// Tutorial Phase 4: Integrate a Black-box verilog version of the SHA3 RoCC accelerator
+class TutorialSha3BlackBoxConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+
+  new testchipip.WithTSI ++
+  new chipyard.config.WithNoGPIO ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithRenumberHarts ++
+  new chipyard.config.WithUART ++
+
+  // Uncomment these lines once SHA3 is integrated
+  // new sha3.WithSha3BlackBox ++ // Specify we want the Black-box verilog version of Sha3 Ctrl
+  // new sha3.WithSha3Accel ++
+
+  // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.system.BaseConfig
+)

generators/chipyard/src/main/scala/example/GCD.scala

@@ -1,11 +1,11 @@
-package example
+package chipyard.example
 
 import chisel3._
 import chisel3.util._
 import chisel3.experimental.{IntParam, BaseModule}
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.subsystem.BaseSubsystem
-import freechips.rocketchip.config.{Parameters, Field}
+import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper.{HasRegMap, RegField}
 import freechips.rocketchip.tilelink._
@@ -125,7 +125,7 @@ trait GCDModule extends HasRegMap {
   gcd.valid := impl.io.output_valid
   impl.io.output_ready := gcd.ready
 
-  status := Cat(impl.io.input_ready, impl.io.output_ready)
+  status := Cat(impl.io.input_ready, impl.io.output_valid)
   io.gcd_busy := impl.io.busy
 
   regmap(
@@ -198,3 +198,10 @@ trait CanHavePeripheryGCDModuleImp extends LazyModuleImp {
 }
 
 // DOC include end: GCD imp trait
+
+
+// DOC include start: GCD config fragment
+class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => {
+  case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox))
+})
+// DOC include end: GCD config fragment

generators/chipyard/src/main/scala/example/InitZero.scala

@@ -1,9 +1,9 @@
-package example
+package chipyard.example
 
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
-import freechips.rocketchip.config.{Parameters, Field}
+import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
 import testchipip.TLHelper
 
@@ -65,3 +65,10 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem =>
     fbus.fromPort(Some("init-zero"))() := initZero.node
   }
 }
+
+
+// DOC include start: WithInitZero
+class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => {
+  case InitZeroKey => Some(InitZeroConfig(base, size))
+})
+// DOC include end: WithInitZero

generators/chipyard/src/main/scala/example/NodeTypes.scala

@@ -1,4 +1,4 @@
-package example
+package chipyard.example
 
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._

generators/example/src/main/scala/BoomConfigs.scala

@@ -1,111 +0,0 @@
-package example
-
-import chisel3._
-
-import freechips.rocketchip.config.{Config}
-
-// ---------------------
-// BOOM Configs
-// ---------------------
-
-class SmallBoomConfig extends Config(
-  new WithTSI ++                                            // use testchipip serial offchip link
-  new WithNoGPIO ++                                         // no top-level GPIO pins (overrides default set in sifive-blocks)
-  new WithBootROM ++                                        // use testchipip bootrom
-  new WithUART ++                                           // add a UART
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++      // no top-level mmio master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++     // no top-level mmio slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++  // use SiFive L2 cache
-  new boom.common.WithSmallBooms ++                         // 1-wide BOOM
-  new boom.common.WithNBoomCores(1) ++                      // single-core
-  new freechips.rocketchip.system.BaseConfig)               // "base" rocketchip system
-
-class MediumBoomConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new boom.common.WithMediumBooms ++                        // 2-wide BOOM
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class LargeBoomConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new boom.common.WithLargeBooms ++                         // 3-wide BOOM
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class MegaBoomConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new boom.common.WithMegaBooms ++                          // 4-wide BOOM
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class DualSmallBoomConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new boom.common.WithSmallBooms ++
-  new boom.common.WithNBoomCores(2) ++                      // dual-core
-  new freechips.rocketchip.system.BaseConfig)
-
-class SmallRV32BoomConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new boom.common.WithoutBoomFPU ++                        // no fp
-  new boom.common.WithBoomRV32 ++                          // rv32 (32bit)
-  new boom.common.WithSmallBooms ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class HwachaLargeBoomConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new hwacha.DefaultHwachaConfig ++                         // use Hwacha vector accelerator
-  new boom.common.WithLargeBooms ++                         // 3-wide BOOM
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class LoopbackNICBoomConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithLoopbackNIC ++                                   // loopback the NIC
-  new WithIceNIC ++                                        // add IceNIC
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-

generators/example/src/main/scala/ConfigMixins.scala

@@ -1,246 +0,0 @@
-package example
-
-import chisel3._
-import chisel3.util.{log2Up}
-
-import freechips.rocketchip.config.{Field, Parameters, Config}
-import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, CacheBlockBytes}
-import freechips.rocketchip.diplomacy.{LazyModule, ValName}
-import freechips.rocketchip.devices.tilelink.BootROMParams
-import freechips.rocketchip.devices.debug.{Debug}
-import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC, RocketTileParams, MaxHartIdBits}
-import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
-import freechips.rocketchip.util.{AsyncResetReg}
-
-import boom.common.{BoomTilesKey}
-
-import testchipip._
-
-import hwacha.{Hwacha}
-
-import sifive.blocks.devices.gpio._
-import sifive.blocks.devices.uart._
-
-import icenet.{NICKey, NICConfig}
-
-/**
- * TODO: Why do we need this?
- */
-object ConfigValName {
-  implicit val valName = ValName("TestHarness")
-}
-import ConfigValName._
-
-// -----------------------
-// Common Parameter Mixins
-// -----------------------
-
-/**
- * Mixin to add the Chipyard bootrom
- */
-class WithBootROM extends Config((site, here, up) => {
-  case BootROMParams => BootROMParams(
-    contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
-})
-
-// DOC include start: gpio mixin
-/**
- * Mixin to add GPIOs and tie them off outside the DUT
- */
-class WithGPIO extends Config((site, here, up) => {
-  case PeripheryGPIOKey => Seq(
-    GPIOParams(address = 0x10012000, width = 4, includeIOF = false))
-  case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => {
-    val top = up(BuildTop, site)(clock, reset, p, success)
-    // TODO: Currently FIRRTL will error if the GPIO input
-    // pins are unconnected, so tie them to 0.
-    // In future IO cell blackboxes will replace this with
-    // more correct functionality
-    for (gpio <- top.gpio) {
-      for (pin <- gpio.pins) {
-        pin.i.ival := false.B
-      }
-    }
-    top
-  }
-})
-// DOC include end: gpio mixin
-
-/**
- * Mixin to add in UART
- */
-class WithUART extends Config((site, here, up) => {
-  case PeripheryUARTKey => Seq(
-    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256))
-})
-
-/**
- * Mixin to remove any GPIOs
- */
-class WithNoGPIO extends Config((site, here, up) => {
-  case PeripheryGPIOKey => Seq()
-})
-
-// DOC include start: tsi mixin
-/**
- * Mixin to add an offchip TSI link (used for backing memory)
- */
-class WithTSI extends Config((site, here, up) => {
-  case SerialKey => true
-  case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => {
-    val top = up(BuildTop, site)(clock, reset, p, success)
-    success := top.connectSimSerial()
-    top
-  }
-})
-// DOC include end: tsi mixin
-
-/**
- * Mixin to add an DTM (used for dmi or jtag bringup)
- */
-class WithDTM extends Config((site, here, up) => {
-  case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => {
-    val top = up(BuildTop, site)(clock, reset, p, success)
-    top.reset := reset.asBool | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B)
-    Debug.connectDebug(top.debug, top.psd, clock, reset.asBool, success)(p)
-    top
-  }
-})
-
-// DOC include start: GCD mixin
-/**
- * Mixin to add a GCD peripheral
- */
-class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => {
-  case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox))
-})
-// DOC include end: GCD mixin
-
-/**
- * Mixin to add a RTL block device model
- */
-class WithBlockDeviceModel extends Config((site, here, up) => {
-  case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => {
-    val top = up(BuildTop, site)(clock, reset, p, success)
-    top.connectBlockDeviceModel()
-    top
-  }
-})
-
-/**
- * Mixin to add a simulated block device model
- */
-class WithSimBlockDevice extends Config((site, here, up) => {
-  case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => {
-    val top = up(BuildTop, site)(clock, reset, p, success)
-    top.connectSimBlockDevice(clock, reset)
-    top
-  }
-})
-
-// DOC include start: WithInitZero
-/**
- * Mixin to add a peripheral that clears memory
- */
-class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => {
-  case InitZeroKey => Some(InitZeroConfig(base, size))
-})
-// DOC include end: WithInitZero
-
-// ------------------
-// Multi-RoCC Support
-// ------------------
-
-/**
- * Map from a hartId to a particular RoCC accelerator
- */
-case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]])
-
-/**
- * Mixin to enable different RoCCs based on the hartId
- */
-class WithMultiRoCC extends Config((site, here, up) => {
-  case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil)
-})
-
-/**
- * Mixin to add Hwachas to cores based on hart
- *
- * For ex:
- *   Core 0, 1, 2, 3 have been defined earlier
- *     with hartIds of 0, 1, 2, 3 respectively
- *   And you call WithMultiRoCCHwacha(0,1)
- *   Then Core 0 and 1 will get a Hwacha
- *
- * @param harts harts to specify which will get a Hwacha
- */
-class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
-  case MultiRoCCKey => {
-    require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1))
-    up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
-      (i -> Seq((p: Parameters) => {
-        LazyModule(new Hwacha()(p)).suggestName("hwacha")
-      }))
-    }
-  }
-})
-
-
-/**
- * Mixin to add a small Rocket core to the system as a "control" core.
- * Used as an example of a PMU core.
- */
-class WithControlCore extends Config((site, here, up) => {
-  case RocketTilesKey => up(RocketTilesKey, site) :+
-    RocketTileParams(
-      core = RocketCoreParams(
-        useVM = false,
-        fpu = None,
-        mulDiv = Some(MulDivParams(mulUnroll = 8))),
-      btb = None,
-      dcache = Some(DCacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nSets = 64,
-        nWays = 1,
-        nTLBEntries = 4,
-        nMSHRs = 0,
-        blockBytes = site(CacheBlockBytes))),
-      icache = Some(ICacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nSets = 64,
-        nWays = 1,
-        nTLBEntries = 4,
-        blockBytes = site(CacheBlockBytes))),
-      hartId = up(RocketTilesKey, site).size + up(BoomTilesKey, site).size
-    )
-  case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
-})
-
-/**
- * Mixin to add an IceNIC
- */
-class WithIceNIC(inBufFlits: Int = 1800, usePauser: Boolean = false)
-    extends Config((site, here, up) => {
-  case NICKey => Some(NICConfig(
-    inBufFlits = inBufFlits,
-    usePauser = usePauser,
-    checksumOffload = true))
-})
-
-/**
- * Mixin to loopback the IceNIC
- */
-class WithLoopbackNIC extends Config((site, here, up) => {
-  case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => {
-    val top = up(BuildTop, site)(clock, reset, p, success)
-    top.connectNicLoopback()
-    top
-  }
-})
-
-/**
- * Mixin to add a backing scratchpad (default size 4MB)
- */
-class WithBackingScratchpad(base: BigInt = 0x80000000L, mask: BigInt = ((4 << 20) - 1)) extends Config((site, here, up) => {
-  case BackingScratchpadKey => Some(BackingScratchpadParams(base, mask))
-})

generators/example/src/main/scala/HeteroConfigs.scala

@@ -1,148 +0,0 @@
-package example
-
-import chisel3._
-
-import freechips.rocketchip.config.{Config}
-
-// ---------------------
-// Heterogenous Configs
-// ---------------------
-
-class LargeBoomAndRocketConfig extends Config(
-  new WithTSI ++                                           // use testchipip serial offchip link
-  new WithNoGPIO ++                                        // no top-level GPIO pins (overrides default set in sifive-blocks)
-  new WithBootROM ++                                       // default bootrom
-  new WithUART ++                                          // add a UART
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive l2
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++     // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++    // no top-level MMIO slave port (overrides default set in rocketchip)
-  new boom.common.WithRenumberHarts ++                     // avoid hartid overlap
-  new boom.common.WithLargeBooms ++                        // 3-wide boom
-  new boom.common.WithNBoomCores(1) ++                     // single-core boom
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // single-core rocket
-  new freechips.rocketchip.system.BaseConfig)              // "base" rocketchip system
-
-class SmallBoomAndRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithSmallBooms ++                        // 1-wide boom
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-// DOC include start: BoomAndRocketWithHwacha
-class HwachaLargeBoomAndHwachaRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new hwacha.DefaultHwachaConfig ++                      // add hwacha to all harts
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-// DOC include end: BoomAndRocketWithHwacha
-
-class RoccLargeBoomAndRoccRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithRoccExample ++  // add example rocc accelerator to all harts
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class DualLargeBoomAndRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.WithNBoomCores(2) ++                  // 2-boom cores
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-// DOC include start: DualBoomAndRocketOneHwacha
-class DualLargeBoomAndHwachaRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new WithMultiRoCC ++                                  // support heterogeneous rocc
-  new WithMultiRoCCHwacha(2) ++                         // override: put hwacha on hart-2 (rocket)
-  new hwacha.DefaultHwachaConfig ++                     // setup hwacha on all harts
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.WithNBoomCores(2) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-// DOC include end: DualBoomAndRocketOneHwacha
-
-class LargeBoomAndRV32RocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.subsystem.WithRV32 ++        // use 32-bit rocket
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-// DOC include start: DualBoomAndRocket
-class DualLargeBoomAndDualRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.WithNBoomCores(2) ++                   // 2 boom cores
-  new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores
-  new freechips.rocketchip.system.BaseConfig)
-// DOC include end: DualBoomAndRocket
-
-class MultiCoreWithControlCoreConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new WithControlCore ++                                 // add small control core (last hartid)
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.WithNBoomCores(2) ++                   // 2 normal boom cores
-  new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 normal rocket cores
-  new freechips.rocketchip.system.BaseConfig)

generators/example/src/main/scala/RocketConfigs.scala

@@ -1,241 +0,0 @@
-package example
-
-import chisel3._
-
-import freechips.rocketchip.config.{Config}
-
-// --------------
-// Rocket Configs
-// --------------
-
-class RocketConfig extends Config(
-  new WithTSI ++                                           // use testchipip serial offchip link
-  new WithNoGPIO ++                                        // no top-level GPIO pins (overrides default set in sifive-blocks)
-  new WithBootROM ++                                       // use default bootrom
-  new WithUART ++                                          // add a UART
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++     // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++    // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // single rocket-core
-  new freechips.rocketchip.system.BaseConfig)              // "base" rocketchip system
-
-class HwachaRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new hwacha.DefaultHwachaConfig ++                        // use Hwacha vector accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-// DOC include start: GemminiRocketConfig
-class GemminiRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new gemmini.DefaultGemminiConfig ++                        // use Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-// DOC include end: GemminiRocketConfig
-
-class RoccRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithRoccExample ++    // use example RoCC-based accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-// DOC include start: JtagRocket
-class jtagRocketConfig extends Config(
-  new WithDTM ++                                           // use top with dtm
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithJtagDTM ++        // enable communicating with the DTM using jtag
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-// DOC include end: JtagRocket
-
-// DOC include start: DmiRocket
-class dmiRocketConfig extends Config(
-  new WithDTM ++                                           // use top with dtm
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-// DOC include end: DmiRocket
-
-// DOC include start: GCDTLRocketConfig
-class GCDTLRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithUART ++
-  new WithGCD(useAXI4=false, useBlackBox=false) ++          // Use GCD Chisel, connect Tilelink
-  new WithBootROM ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-// DOC include end: GCDTLRocketConfig
-
-// DOC include start: GCDAXI4BlackBoxRocketConfig
-class GCDAXI4BlackBoxRocketConfig extends Config(
-  new WithTSI ++
-  new WithUART ++
-  new WithNoGPIO ++
-  new WithGCD(useAXI4=true, useBlackBox=true) ++          // Use GCD blackboxed verilog, connect by AXI4->Tilelink
-  new WithBootROM ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-// DOC include end: GCDAXI4BlackBoxRocketConfig
-
-class SimBlockDeviceRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new testchipip.WithBlockDevice ++                        // add block-device module to peripherybus
-  new WithSimBlockDevice ++                                // use top with block-device IOs and connect to simblockdevice
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class BlockDeviceModelRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new testchipip.WithBlockDevice ++                        // add block-device module to periphery bus
-  new WithBlockDeviceModel ++                              // use top with block-device IOs and connect to a blockdevicemodel
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-// DOC include start: GPIORocketConfig
-class GPIORocketConfig extends Config(
-  new WithTSI ++
-  new WithGPIO ++                                          // add GPIOs to the peripherybus
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-// DOC include end: GPIORocketConfig
-
-class DualCoreRocketConfig extends Config(
-  new WithTSI ++
-  new WithBootROM ++
-  new WithUART ++
-  new WithNoGPIO ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNBigCores(2) ++   // dual-core (2 RocketTiles)
-  new freechips.rocketchip.system.BaseConfig)
-
-class RV32RocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithRV32 ++           // set RocketTiles to be 32-bit
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class GB1MemoryRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-// DOC include start: Sha3Rocket
-class Sha3RocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-// DOC include end: Sha3Rocket
-
-// DOC include start: InitZeroRocketConfig
-class InitZeroRocketConfig extends Config(
-  new WithInitZero(0x88000000L, 0x1000L) ++                // add InitZero
-  new WithNoGPIO ++
-  new WithTSI ++
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-// DOC include end: InitZeroRocketConfig
-
-class LoopbackNICRocketConfig extends Config(
-  new WithTSI ++
-  new WithIceNIC ++                                         // add an IceNIC
-  new WithNoGPIO ++
-  new WithLoopbackNIC ++                                    // loopback the IceNIC
-  new WithBootROM ++
-  new WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class ScratchpadRocketConfig extends Config(
-  new WithTSI ++
-  new WithNoGPIO ++
-  new WithBootROM ++
-  new WithUART ++
-  new WithBackingScratchpad ++                              // add backing scratchpad
-  new freechips.rocketchip.subsystem.WithNoMemPort ++       // remove offchip mem port
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)

generators/example/src/main/scala/TestHarness.scala

@@ -1,57 +0,0 @@
-package example
-
-import chisel3._
-import chisel3.experimental._
-
-import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}
-
-import freechips.rocketchip.diplomacy.LazyModule
-import freechips.rocketchip.config.{Field, Parameters}
-import freechips.rocketchip.util.GeneratorApp
-import freechips.rocketchip.devices.debug.{Debug}
-
-/**
- * TODO: Why do we need this?
- */
-import ConfigValName._
-
-// -------------------------------
-// BOOM and/or Rocket Test Harness
-// -------------------------------
-
-case object BuildTop extends Field[(Clock, Bool, Parameters, Bool) => TopModule[Top]](
-  (clock: Clock, reset: Bool, p: Parameters, success: Bool) => {
-    val top = Module(LazyModule(new Top()(p)).suggestName("top").module)
-    top.debug.map { debug => debug := DontCare }
-    top
-  }
-)
-
-/**
- * Test harness using TSI to bringup the system
- */
-class TestHarness(implicit val p: Parameters) extends Module {
-  val io = IO(new Bundle {
-    val success = Output(Bool())
-  })
-
-  val dut = p(BuildTop)(clock, reset.toBool, p, io.success)
-  dut.connectSimUARTs()
-  dut.connectSimAXIMem()
-  dut.connectSimAXIMMIO()
-  dut.dontTouchPorts()
-  dut.tieOffInterrupts()
-  dut.l2_frontend_bus_axi4.foreach(axi => {
-    axi.tieoff()
-    experimental.DataMirror.directionOf(axi.ar.ready) match {
-      case core.ActualDirection.Input =>
-        axi.r.bits := DontCare
-        axi.b.bits := DontCare
-      case core.ActualDirection.Output =>
-        axi.aw.bits := DontCare
-        axi.ar.bits := DontCare
-        axi.w.bits := DontCare
-    }
-  })
-
-}

generators/example/src/main/scala/Top.scala

@@ -1,48 +0,0 @@
-package example
-
-import chisel3._
-
-import freechips.rocketchip.subsystem._
-import freechips.rocketchip.system._
-import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.util.DontTouch
-
-import testchipip._
-
-import utilities.{System, SystemModule}
-
-import sifive.blocks.devices.gpio._
-import sifive.blocks.devices.uart._
-
-import icenet.{CanHavePeripheryIceNIC, CanHavePeripheryIceNICModuleImp}
-
-// ------------------------------------
-// BOOM and/or Rocket Top Level Systems
-// ------------------------------------
-
-// DOC include start: Top
-class Top(implicit p: Parameters) extends System
-  with CanHavePeripheryUARTAdapter // Enables optionally adding the UART print adapter
-  with HasPeripheryUART // Enables optionally adding the sifive UART
-  with HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
-  with CanHavePeripheryBlockDevice // Enables optionally adding the block device
-  with CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
-  with CanHavePeripheryGCD // Enables optionally adding the GCD example widget
-  with CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
-  with CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
-  with CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
-{
-  override lazy val module = new TopModule(this)
-}
-
-class TopModule[+L <: Top](l: L) extends SystemModule(l)
-  with HasPeripheryGPIOModuleImp
-  with HasPeripheryUARTModuleImp
-  with CanHavePeripheryBlockDeviceModuleImp
-  with CanHavePeripheryGCDModuleImp
-  with CanHavePeripherySerialModuleImp
-  with CanHavePeripheryIceNICModuleImp
-  with CanHavePeripheryUARTAdapterModuleImp
-  with DontTouch
-// DOC include end: Top

generators/example/src/main/scala/TopCakes.scala

@@ -1,27 +0,0 @@
-package example
-
-import chisel3._
-
-import freechips.rocketchip.subsystem.BaseSubsystem
-import freechips.rocketchip.config.{Field}
-import freechips.rocketchip.diplomacy.{LazyModule, AddressSet}
-import freechips.rocketchip.tilelink.{TLRAM}
-
-case class BackingScratchpadParams(
-  base: BigInt,
-  mask: BigInt)
-
-case object BackingScratchpadKey extends Field[Option[BackingScratchpadParams]](None)
-
-/**
- * Trait to add a scratchpad on the mbus
- */
-trait CanHaveBackingScratchpad { this: BaseSubsystem =>
-  private val portName = "Backing-Scratchpad"
-
-  val spadOpt = p(BackingScratchpadKey).map { param =>
-    val spad = LazyModule(new TLRAM(address=AddressSet(param.base, param.mask), beatBytes=mbus.beatBytes))
-    mbus.toVariableWidthSlave(Some(portName)) { spad.node }
-    spad
-  }
-}

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -3,53 +3,53 @@
 package firesim.firesim
 
 import chisel3._
+import chisel3.experimental.annotate
 
-import freechips.rocketchip.config.{Field, Config}
+import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
 import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
+import freechips.rocketchip.tile.{RocketTile}
 import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
 
-import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp}
-import icenet.HasPeripheryIceNICModuleImpValidOnly
+import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp}
+import icenet.CanHavePeripheryIceNICModuleImp
 
 import junctions.{NastiKey, NastiParameters}
 import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
+import midas.targetutils.{MemModelAnnotation}
 import firesim.bridges._
 import firesim.configs.MemModelKey
-import firesim.util.RegisterBridgeBinder
 import tracegen.HasTraceGenTilesModuleImp
+import ariane.ArianeTile
 
-class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
-  target.debug.foreach(_.clockeddmi.foreach({ cdmi =>
-    cdmi.dmi.req.valid := false.B
-    cdmi.dmi.req.bits := DontCare
-    cdmi.dmi.resp.ready := false.B
-    cdmi.dmiClock := false.B.asClock
-    cdmi.dmiReset := false.B
-  }))
-  Seq()
+import boom.common.{BoomTile}
+
+import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
+import chipyard.HasChipyardTilesModuleImp
+
+class WithSerialBridge extends OverrideIOBinder({
+  (c, r, s, target: CanHavePeripherySerialModuleImp) =>
+    target.serial.map(s => SerialBridge(target.clock, s)(target.p)).toSeq
 })
 
-class WithSerialBridge extends RegisterBridgeBinder({
-  case target: CanHavePeripherySerialModuleImp => Seq(SerialBridge(target.clock, target.serial.get)(target.p))
+class WithNICBridge extends OverrideIOBinder({
+  (c, r, s, target: CanHavePeripheryIceNICModuleImp) =>
+    target.net.map(n => NICBridge(target.clock, n)(target.p)).toSeq
 })
 
-class WithNICBridge extends RegisterBridgeBinder({
-  case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.clock, target.net)(target.p))
+class WithUARTBridge extends OverrideIOBinder({
+  (c, r, s, target: HasPeripheryUARTModuleImp) =>
+    target.uart.map(u => UARTBridge(target.clock, u)(target.p)).toSeq
 })
 
-class WithUARTBridge extends RegisterBridgeBinder({
-  case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(target.clock, u)(target.p))
+class WithBlockDeviceBridge extends OverrideIOBinder({
+  (c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) =>
+    target.bdev.map(b => BlockDevBridge(target.clock, b, target.reset.toBool)(target.p)).toSeq
 })
 
-class WithBlockDeviceBridge extends RegisterBridgeBinder({
-  case target: CanHavePeripheryBlockDeviceModuleImp =>
-    Seq(BlockDevBridge(target.clock, target.bdev.get, target.reset.toBool)(target.p))
-})
-
-class WithFASEDBridge extends RegisterBridgeBinder({
-  case t: CanHaveMasterAXI4MemPortModuleImp =>
+class WithFASEDBridge extends OverrideIOBinder({
+  (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => {
     implicit val p = t.p
     (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
       (io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
@@ -60,22 +60,58 @@ class WithFASEDBridge extends RegisterBridgeBinder({
           CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge))))
       })
     }).toSeq
+  }
 })
 
-class WithTracerVBridge extends Config((_,_,_) => { case InstantiateTracerVBridges => true })
+class WithTracerVBridge extends OverrideIOBinder({
+  (c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO match {
+    case Some(t) => t.traces.map(tileTrace => TracerVBridge(tileTrace)(target.p))
+    case None    => Nil
+  }
+})
 
-class WithTraceGenBridge extends RegisterBridgeBinder({
-  case target: HasTraceGenTilesModuleImp =>
+
+class WithTraceGenBridge extends OverrideIOBinder({
+  (c, r, s, target: HasTraceGenTilesModuleImp) =>
     Seq(GroundTestBridge(target.clock, target.success)(target.p))
 })
 
+class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
+  (c, r, s, target: HasChipyardTilesModuleImp) => {
+    target.outer.tiles.map {
+      case r: RocketTile => {
+        annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
+        r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
+      }
+      case b: BoomTile => {
+        val core = b.module.core
+        core.iregfile match {
+          case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
+          case _ => Nil
+        }
+        if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
+          case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
+          case _ => Nil
+        }
+      }
+      case a: ArianeTile => Nil
+    }
+    Nil
+  }
+})
+
+
+
 // Shorthand to register all of the provided bridges above
 class WithDefaultFireSimBridges extends Config(
-  new WithTiedOffDebug ++
+  new chipyard.iobinders.WithGPIOTiedOff ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
   new WithSerialBridge ++
   new WithNICBridge ++
   new WithUARTBridge ++
   new WithBlockDeviceBridge ++
   new WithFASEDBridge ++
+  new WithFireSimMultiCycleRegfile ++
   new WithTracerVBridge
 )

generators/firechip/src/main/scala/FireSim.scala

@@ -0,0 +1,64 @@
+//See LICENSE for license details.
+
+package firesim.firesim
+
+import chisel3._
+
+import freechips.rocketchip.config.{Field, Config, Parameters}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+import freechips.rocketchip.subsystem.{HasTiles}
+import freechips.rocketchip.util.{ResetCatchAndSync}
+
+import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock}
+
+import chipyard.{BuildTop}
+import chipyard.iobinders.{IOBinders}
+
+// Determines the number of times to instantiate the DUT in the harness.
+// Subsumes legacy supernode support
+case object NumNodes extends Field[Int](1)
+
+class WithNumNodes(n: Int) extends Config((pname, site, here) => {
+  case NumNodes => n
+})
+
+case class FireSimClockParameters(additionalClocks: Seq[RationalClock]) {
+  def numClocks(): Int = additionalClocks.size + 1
+}
+case object FireSimClockKey extends Field[FireSimClockParameters](FireSimClockParameters(Seq()))
+
+trait HasAdditionalClocks extends LazyModuleImp {
+  val clocks = IO(Vec(p(FireSimClockKey).numClocks, Input(Clock())))
+}
+
+trait HasFireSimClockingImp extends HasAdditionalClocks {
+  val outer: HasTiles
+  val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match {
+    case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool))
+    case None => (clocks(0), reset)
+  }
+
+  outer.tiles.foreach({ case tile =>
+    tile.module.clock := tileClock
+    tile.module.reset := tileReset
+  })
+}
+
+class FireSim[T <: LazyModule](implicit val p: Parameters) extends RawModule {
+  val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*))
+  val refClock = clockBridge.io.clocks(0)
+  val reset = WireInit(false.B)
+  withClockAndReset(refClock, reset) {
+    // Instantiate multiple instances of the DUT to implement supernode
+    val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p))
+    val peekPokeBridge = PeekPokeBridge(refClock, reset)
+    // A Seq of partial functions that will instantiate the right bridge only
+    // if that Mixin trait is present in the target's class instance
+    //
+    // Apply each partial function to each DUT instance
+    for ((target) <- targets) {
+      p(IOBinders).values.map(fn => fn(refClock, reset.asBool, false.B, target))
+    }
+    targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks })
+  }
+}

generators/firechip/src/main/scala/Generator.scala

@@ -20,12 +20,13 @@ import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGenerat
 
 import scala.util.Try
 
-import utilities.TestSuiteHelper
+import chipyard.TestSuiteHelper
 
 trait HasTestSuites {
   def addTestSuites(targetName: String, params: Parameters) {
     TestSuiteHelper.addRocketTestSuites(params)
     TestSuiteHelper.addBoomTestSuites(params)
+    TestSuiteHelper.addArianeTestSuites(params)
     TestGeneration.addSuite(FastBlockdevTests)
     TestGeneration.addSuite(SlowBlockdevTests)
     if (!targetName.contains("NoNIC"))
@@ -61,7 +62,7 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike {
   override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   lazy val generatorArgs = GeneratorArgs(args)
   lazy val genDir = new File(names.targetDir)
-  // The only reason this is not generateFirrtl; generateAnno is that we need to use a different 
+  // The only reason this is not generateFirrtl; generateAnno is that we need to use a different
   // JsonProtocol to properly write out the annotations. Fix once the generated are unified
   elaborate
   generateTestSuiteMakefrags

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -2,6 +2,7 @@ package firesim.firesim
 
 import java.io.File
 
+import chisel3._
 import chisel3.util.{log2Up}
 import freechips.rocketchip.config.{Parameters, Config}
 import freechips.rocketchip.groundtest.TraceGenParams
@@ -12,17 +13,21 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
 import freechips.rocketchip.diplomacy.{RationalCrossing}
+import freechips.rocketchip.diplomacy.LazyModule
 import boom.common.{BoomTilesKey, BoomCrossingKey}
-import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey}
+import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import scala.math.{min, max}
 import tracegen.TraceGenKey
 import icenet._
+import ariane.ArianeTilesKey
+import testchipip.WithRingSystemBus
 
 import firesim.bridges._
-import firesim.util.{WithNumNodes, FireSimClockKey, FireSimClockParameters}
+import midas.widgets.{RationalClock}
 import firesim.configs._
-import midas.widgets.RationalClock
+import chipyard.{BuildTop}
+import chipyard.config.ConfigValName._
 
 class WithBootROM extends Config((site, here, up) => {
   case BootROMParams => {
@@ -42,312 +47,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) =>
   case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq)
 })
 
-class WithUARTKey extends Config((site, here, up) => {
-  case PeripheryUARTKey => List(UARTParams(
-     address = BigInt(0x54000000L),
-     nTxEntries = 256,
-     nRxEntries = 256))
-})
-
-class WithSerial extends Config((site, here, up) => {
-  case SerialKey => true
-})
-
-class WithBlockDevice extends Config(new testchipip.WithBlockDevice)
-
-class WithNICKey extends Config((site, here, up) => {
-  case NICKey => Some(NICConfig(
-    inBufFlits = 8192,
-    ctrlQueueDepth = 64,
-    checksumOffload = true))
-})
-
-class WithRocketL2TLBs(entries: Int) extends Config((site, here, up) => {
-  case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
-    core = tile.core.copy(
-      nL2TLBEntries = entries
-    )
-  ))
-})
-
-class WithPerfCounters extends Config((site, here, up) => {
-  case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
-    core = tile.core.copy(nPerfCounters = 29)
-  ))
-})
-
-class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(
-    core = tile.core.copy(nL2TLBEntries = entries)
-  ))
-})
-
-class WithBoomEnableTrace extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
-})
-
-// Disables clock-gating; doesn't play nice with our FAME-1 pass
-class WithoutClockGating extends Config((site, here, up) => {
-  case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
-})
-
-// Testing configurations
-// This enables printfs used in testing
-class WithScalaTestFeatures extends Config((site, here, up) => {
-    case PrintTracePort => true
-})
-
-// FASED Config Aliases. This to enable config generation via "_" concatenation
-// which requires that all config classes be defined in the same package
-class DDR3FRFCFS extends FRFCFS16GBQuadRank
-class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
-
-// L2 Config Aliases. For use with "_" concatenation
-class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache
-
-/*******************************************************************************
-* Full TARGET_CONFIG configurations. These set parameters of the target being
-* simulated.
-*
-* In general, if you're adding or removing features from any of these, you
-* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
-* will store this name as part of the tags for the AGFI, so that later you can
-* reconstruct what is in a particular AGFI. These tags are also used to
-* determine which driver to build.
-*******************************************************************************/
-class FireSimRocketChipConfig extends Config(
-  new WithBootROM ++
-  new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
-  new WithExtMemSize(0x400000000L) ++ // 16GB
-  new WithoutTLMonitors ++
-  new WithUARTKey ++
-  new WithNICKey ++
-  new WithSerial ++
-  new WithBlockDevice ++
-  new WithRocketL2TLBs(1024) ++
-  new WithPerfCounters ++
-  new WithoutClockGating ++
-  new WithDefaultMemModel ++
-  new WithDefaultFireSimBridges ++
-  new freechips.rocketchip.system.DefaultConfig)
-
-class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
-  case RocketTilesKey => List.tabulate(n)(i => up(RocketTilesKey).head.copy(hartId = i))
-})
-
-// single core config
-class FireSimRocketChipSingleCoreConfig extends Config(new FireSimRocketChipConfig)
-
-// dual core config
-class FireSimRocketChipDualCoreConfig extends Config(
-  new WithNDuplicatedRocketCores(2) ++
-  new FireSimRocketChipSingleCoreConfig)
-
-// quad core config
-class FireSimRocketChipQuadCoreConfig extends Config(
-  new WithNDuplicatedRocketCores(4) ++
-  new FireSimRocketChipSingleCoreConfig)
-
-// hexa core config
-class FireSimRocketChipHexaCoreConfig extends Config(
-  new WithNDuplicatedRocketCores(6) ++
-  new FireSimRocketChipSingleCoreConfig)
-
-// octa core config
-class FireSimRocketChipOctaCoreConfig extends Config(
-  new WithNDuplicatedRocketCores(8) ++
-  new FireSimRocketChipSingleCoreConfig)
-
-// SHA-3 accelerator config
-class FireSimRocketChipSha3L2Config extends Config(
-  new WithInclusiveCache ++
-  new sha3.WithSha3Accel ++
-  new WithNBigCores(1) ++
-  new FireSimRocketChipConfig)
-
-// SHA-3 accelerator config with synth printfs enabled
-class FireSimRocketChipSha3L2PrintfConfig extends Config(
-  new WithInclusiveCache ++
-  new sha3.WithSha3Printf ++ 
-  new sha3.WithSha3Accel ++
-  new WithNBigCores(1) ++
-  new FireSimRocketChipConfig)
-
-class FireSimBoomConfig extends Config(
-  new WithBootROM ++
-  new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
-  new WithExtMemSize(0x400000000L) ++ // 16GB
-  new WithoutTLMonitors ++
-  new WithUARTKey ++
-  new WithNICKey ++
-  new WithSerial ++
-  new WithBlockDevice ++
-  new WithBoomEnableTrace ++
-  new WithBoomL2TLBs(1024) ++
-  new WithoutClockGating ++
-  new WithDefaultMemModel ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.WithNBoomCores(1) ++
-  new WithDefaultFireSimBridges ++
-  new freechips.rocketchip.system.BaseConfig
-)
-
-// A safer implementation than the one in BOOM in that it
-// duplicates whatever BOOMTileKey.head is present N times. This prevents
-// accidentally (and silently) blowing away configurations that may change the
-// tile in the "up" view
-class WithNDuplicatedBoomCores(n: Int) extends Config((site, here, up) => {
-  case BoomTilesKey => List.tabulate(n)(i => up(BoomTilesKey).head.copy(hartId = i))
-  case MaxHartIdBits => log2Up(site(BoomTilesKey).size)
-})
-
-class FireSimBoomDualCoreConfig extends Config(
-  new WithNDuplicatedBoomCores(2) ++
-  new FireSimBoomConfig)
-
-class FireSimBoomQuadCoreConfig extends Config(
-  new WithNDuplicatedBoomCores(4) ++
-  new FireSimBoomConfig)
-
-//**********************************************************************************
-//* Heterogeneous Configurations
-//*********************************************************************************/
-
-// dual core config (rocket + small boom)
-class FireSimRocketBoomConfig extends Config(
-  new WithBoomL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it)
-  new boom.common.WithRenumberHarts ++ // fix hart numbering
-  new boom.common.WithSmallBooms ++ // change single BOOM to small
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core
-  new FireSimBoomConfig
-)
-
-//**********************************************************************************
-//* Gemmini Configurations
-//*********************************************************************************/
-
-// Gemmini systolic accelerator default config
-class FireSimRocketChipGemminiL2Config extends Config(
-  new WithInclusiveCache ++
-  new gemmini.DefaultGemminiConfig ++
-  new WithNBigCores(1) ++
-  new FireSimRocketChipConfig)
-
-
-//**********************************************************************************
-//* Supernode Configurations
-//*********************************************************************************/
-
-class SupernodeFireSimRocketChipConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipConfig)
-
-class SupernodeFireSimRocketChipSingleCoreConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipSingleCoreConfig)
-
-class SupernodeSixNodeFireSimRocketChipSingleCoreConfig extends Config(
-  new WithNumNodes(6) ++
-  new WithExtMemSize(0x40000000L) ++ // 1GB
-  new FireSimRocketChipSingleCoreConfig)
-
-class SupernodeEightNodeFireSimRocketChipSingleCoreConfig extends Config(
-  new WithNumNodes(8) ++
-  new WithExtMemSize(0x40000000L) ++ // 1GB
-  new FireSimRocketChipSingleCoreConfig)
-
-class SupernodeFireSimRocketChipDualCoreConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipDualCoreConfig)
-
-class SupernodeFireSimRocketChipQuadCoreConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipQuadCoreConfig)
-
-class SupernodeFireSimRocketChipHexaCoreConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipHexaCoreConfig)
-
-class SupernodeFireSimRocketChipOctaCoreConfig extends Config(
-  new WithNumNodes(4) ++
-  new WithExtMemSize(0x200000000L) ++ // 8GB
-  new FireSimRocketChipOctaCoreConfig)
-
-class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
-    extends Config((site, here, up) => {
-  case TraceGenKey => params.map { dcp => TraceGenParams(
-    dcache = Some(dcp),
-    wordBits = site(XLen),
-    addrBits = 48,
-    addrBag = {
-      val nSets = dcp.nSets
-      val nWays = dcp.nWays
-      val blockOffset = site(SystemBusKey).blockOffset
-      val nBeats = min(2, site(SystemBusKey).blockBeats)
-      val beatBytes = site(SystemBusKey).beatBytes
-      List.tabulate(2 * nWays) { i =>
-        Seq.tabulate(nBeats) { j =>
-          BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
-        }
-      }.flatten
-    },
-    maxRequests = nReqs,
-    memStart = site(ExtMem).get.master.base,
-    numGens = params.size)
-  }
-  case MaxHartIdBits => log2Up(params.size)
-})
-
-class FireSimTraceGenConfig extends Config(
-  new WithTraceGen(
-    List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
-  new WithTraceGenBridge ++
-  new FireSimRocketChipConfig)
-
-class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
-    extends Config((site, here, up) => {
-  case TraceGenKey => params.map { dcp => TraceGenParams(
-    dcache = Some(dcp),
-    wordBits = site(XLen),
-    addrBits = 48,
-    addrBag = {
-      val sbp = site(SystemBusKey)
-      val l2p = site(InclusiveCacheKey)
-      val nSets = max(l2p.sets, dcp.nSets)
-      val nWays = max(l2p.ways, dcp.nWays)
-      val nBanks = site(BankedL2Key).nBanks
-      val blockOffset = sbp.blockOffset
-      val nBeats = min(2, sbp.blockBeats)
-      val beatBytes = sbp.beatBytes
-      List.tabulate(2 * nWays) { i =>
-        Seq.tabulate(nBeats) { j =>
-          BigInt((j * beatBytes) + ((i * nSets * nBanks) << blockOffset))
-        }
-      }.flatten
-    },
-    maxRequests = nReqs,
-    memStart = site(ExtMem).get.master.base,
-    numGens = params.size)
-  }
-  case MaxHartIdBits => log2Up(params.size)
-})
-
-class FireSimTraceGenL2Config extends Config(
-  new WithL2TraceGen(
-    List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
-  new WithInclusiveCache(
-    nBanks = 4,
-    capacityKB = 1024,
-    outerLatencyCycles = 50) ++
-  new WithTraceGenBridge ++
-  new FireSimRocketChipConfig)
-
-
 class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, here, up) => {
   case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor)))
   case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
@@ -360,15 +59,147 @@ class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, her
 
 class HalfRateUncore extends WithRationalTiles(2,1)
 
-// Eagle X Mock Configs
-class EagleMockConfig(numCores: Int) extends Config(
-  new WithBootROM ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks = 16, capacityKB = 8192) ++
-  new hwacha.DefaultHwachaConfig ++                        // use Hwacha vector accelerator
-  new WithNBigCores(numCores) ++
-  new FireSimRocketChipConfig)
 
-class EX20C extends EagleMockConfig(20)
-class EX16C extends EagleMockConfig(16)
-class EX12C extends EagleMockConfig(12)
-class EX8C extends EagleMockConfig(8)
+class WithPerfCounters extends Config((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
+    core = tile.core.copy(nPerfCounters = 29)
+  ))
+})
+
+
+// Disables clock-gating; doesn't play nice with our FAME-1 pass
+class WithoutClockGating extends Config((site, here, up) => {
+  case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
+})
+
+// Testing configurations
+// This enables printfs used in testing
+class WithScalaTestFeatures extends Config((site, here, up) => {
+  case TracePortKey => up(TracePortKey, site).map(_.copy(print = true))
+})
+
+
+// FASED Config Aliases. This to enable config generation via "_" concatenation
+// which requires that all config classes be defined in the same package
+class DDR3FRFCFS extends FRFCFS16GBQuadRank
+class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
+
+class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
+
+
+
+// Enables tracing on all cores
+class WithTraceIO extends Config((site, here, up) => {
+  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+  case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
+  case TracePortKey => Some(TracePortParams())
+})
+
+
+// Tweaks that are generally applied to all firesim configs
+class WithFireSimConfigTweaks extends Config(
+  // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
+  new WithBootROM ++
+  // Optional*: Removing this will require target-software changes to properly capture UART output
+  new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
+  // Required: Existing FAME-1 transform cannot handle black-box clock gates
+  new WithoutClockGating ++
+  // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix)
+  new WithoutTLMonitors ++
+  // Optional: Adds IO to attach tracerV bridges
+  new WithTraceIO ++
+  // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
+  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
+  // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
+  // for signalling simulation termination under simulation success. This fragment can
+  // be removed if you supply an auxiliary bridge that signals simulation termination
+  new testchipip.WithTSI ++
+  // Optional: Removing this will require using an initramfs under linux
+  new testchipip.WithBlockDevice ++
+  // Required*:
+  new chipyard.config.WithUART
+)
+
+/*******************************************************************************
+* Full TARGET_CONFIG configurations. These set parameters of the target being
+* simulated.
+*
+* In general, if you're adding or removing features from any of these, you
+* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
+* will store this name as part of the tags for the AGFI, so that later you can
+* reconstruct what is in a particular AGFI. These tags are also used to
+* determine which driver to build.
+ *******************************************************************************/
+
+//*****************************************************************
+// Rocket configs, base off chipyard's RocketConfig
+//*****************************************************************
+// DOC include start: firesimconfig
+class FireSimRocketConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.RocketConfig)
+// DOC include end: firesimconfig
+
+class FireSimQuadRocketConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.QuadRocketConfig)
+
+
+//*****************************************************************
+// Boom config, base off chipyard's LargeBoomConfig
+//*****************************************************************
+class FireSimLargeBoomConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.LargeBoomConfig)
+
+
+//********************************************************************
+// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
+//********************************************************************
+class FireSimLargeBoomAndRocketConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.LargeBoomAndRocketConfig)
+
+//******************************************************************
+// Gemmini NN accel config, base off chipyard's GemminiRocketConfig
+//******************************************************************
+class FireSimGemminiRocketConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.GemminiRocketConfig)
+
+//******************************************************************
+// Configuration with Ring topology SystemBus
+//******************************************************************
+class FireSimRingSystemBusRocketConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.RingSystemBusRocketConfig)
+
+//**********************************************************************************
+// Supernode Configurations, base off chipyard's RocketConfig
+//**********************************************************************************
+class SupernodeFireSimRocketConfig extends Config(
+  new WithNumNodes(4) ++
+  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8 GB
+  new FireSimRocketConfig)
+
+//**********************************************************************************
+//* Ariane Configurations
+//*********************************************************************************/
+
+class FireSimArianeConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.ArianeConfig)

generators/firechip/src/main/scala/TargetMixins.scala

@@ -1,92 +0,0 @@
-package firesim.firesim
-
-import chisel3._
-import chisel3.util.Cat
-import chisel3.experimental.annotate
-import freechips.rocketchip.config.{Field, Parameters}
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.subsystem._
-import freechips.rocketchip.amba.axi4._
-import freechips.rocketchip.util._
-import freechips.rocketchip.tile.RocketTile
-import freechips.rocketchip.subsystem._
-import freechips.rocketchip.rocket.TracedInstruction
-import firesim.bridges.{TracerVBridge}
-import firesim.util.{HasAdditionalClocks, FireSimClockKey}
-
-import midas.targetutils.MemModelAnnotation
-import midas.widgets.RationalClock
-
-import boom.common.BoomTile
-
-/* Wires out tile trace ports to the top; and wraps them in a Bundle that the
- * TracerV bridge can match on.
- */
-case object PrintTracePort extends Field[Boolean](false)
-case object InstantiateTracerVBridges extends Field[Boolean](false)
-
-trait HasTraceIO {
-  this: HasTiles =>
-  val module: HasTraceIOImp
-
-  // Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp
-  val tileTraceNodes = tiles.map({ tile =>
-    val node = BundleBridgeSink[Vec[TracedInstruction]]
-    node := tile.traceNode
-    node
-  })
-}
-
-trait HasTraceIOImp extends LazyModuleImp {
-  val outer: HasTraceIO
-  outer.tileTraceNodes.zipWithIndex.foreach({ case (node, idx) =>
-    if (p(InstantiateTracerVBridges)) {
-      val b = TracerVBridge(node.bundle)
-      // Used for verifying the TracerV bridge
-      if (p(PrintTracePort)) {
-        withClockAndReset(node.bundle.head.clock, node.bundle.head.reset) {
-          val traceprint = WireDefault(0.U(512.W))
-          // The reverse is here to match the behavior the Cat used in the bridge
-          traceprint := b.io.traces.reverse.asUInt
-          printf(s"TRACEPORT ${idx}: %x\n", traceprint)
-        }
-      }
-    }
-  })
-}
-
-trait CanHaveMultiCycleRegfileImp {
-  val outer: utilities.HasBoomAndRocketTiles
-
-  outer.tiles.map {
-    case r: RocketTile => {
-      annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
-      r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
-    }
-    case b: BoomTile => {
-      val core = b.module.core
-      core.iregfile match {
-        case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
-        case _ => Nil
-      }
-      if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
-        case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
-        case _ => Nil
-      }
-    }
-  }
-}
-
-trait HasFireSimClockingImp extends HasAdditionalClocks {
-  val outer: HasTiles
-  val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match {
-    case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool))
-    case None => (clocks(0), reset)
-  }
-
-  outer.tiles.foreach({ case tile =>
-    tile.module.clock := tileClock
-    tile.module.reset := tileReset
-  })
-}

generators/firechip/src/main/scala/Targets.scala

@@ -1,119 +0,0 @@
-package firesim.firesim
-
-import chisel3._
-import freechips.rocketchip._
-import freechips.rocketchip.subsystem._
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
-import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.util.{HeterogeneousBag}
-import freechips.rocketchip.amba.axi4.AXI4Bundle
-import freechips.rocketchip.config.{Field, Parameters}
-import freechips.rocketchip.diplomacy.LazyModule
-import utilities.{Subsystem, SubsystemModuleImp}
-import icenet._
-import firesim.util.DefaultFireSimHarness
-import testchipip._
-import testchipip.SerialAdapter.SERIAL_IF_WIDTH
-import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp}
-import sifive.blocks.devices.uart._
-import java.io.File
-
-
-object FireSimValName {
-  implicit val valName = ValName("FireSimHarness")
-}
-import FireSimValName._
-
-/*******************************************************************************
-* Top level DESIGN configurations. These describe the basic instantiations of
-* the designs being simulated.
-*
-* In general, if you're adding or removing features from any of these, you
-* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
-* will store this name as part of the tags for the AGFI, so that later you can
-* reconstruct what is in a particular AGFI. These tags are also used to
-* determine which driver to build.
-*******************************************************************************/
-
-class FireSimDUT(implicit p: Parameters) extends Subsystem
-    with HasHierarchicalBusTopology
-    with CanHaveMasterAXI4MemPort
-    with HasPeripheryBootROM
-    with CanHavePeripherySerial
-    with HasPeripheryUART
-    with CanHavePeripheryIceNIC
-    with CanHavePeripheryBlockDevice
-    with HasTraceIO
-{
-  override lazy val module = new FireSimModuleImp(this)
-}
-
-class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l)
-    with HasRTCModuleImp
-    with CanHaveMasterAXI4MemPortModuleImp
-    with HasPeripheryBootROMModuleImp
-    with CanHavePeripherySerialModuleImp
-    with HasPeripheryUARTModuleImp
-    with HasPeripheryIceNICModuleImpValidOnly
-    with CanHavePeripheryBlockDeviceModuleImp
-    with HasTraceIOImp
-    with HasFireSimClockingImp
-    with CanHaveMultiCycleRegfileImp
-
-class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)
-
-class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem
-    with HasHierarchicalBusTopology
-    with CanHaveMasterAXI4MemPort
-    with HasPeripheryBootROM
-    with CanHavePeripherySerial
-    with HasPeripheryUART
-    with CanHavePeripheryBlockDevice
-    with HasTraceIO
-{
-  override lazy val module = new FireSimNoNICModuleImp(this)
-}
-
-class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModuleImp(l)
-    with HasRTCModuleImp
-    with CanHaveMasterAXI4MemPortModuleImp
-    with HasPeripheryBootROMModuleImp
-    with CanHavePeripherySerialModuleImp
-    with HasPeripheryUARTModuleImp
-    with CanHavePeripheryBlockDeviceModuleImp
-    with HasTraceIOImp
-    with HasFireSimClockingImp
-    with CanHaveMultiCycleRegfileImp
-
-class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT)
-
-class FireSimTraceGenDUT(implicit p: Parameters) extends BaseSubsystem
-    with HasHierarchicalBusTopology
-    with HasTraceGenTiles
-    with CanHaveMasterAXI4MemPort {
-  override lazy val module = new FireSimTraceGenModuleImp(this)
-}
-
-class FireSimTraceGenModuleImp(outer: FireSimTraceGenDUT) extends BaseSubsystemModuleImp(outer)
-    with HasTraceGenTilesModuleImp
-    with CanHaveMasterAXI4MemPortModuleImp
-
-class FireSimTraceGen(implicit p: Parameters) extends DefaultFireSimHarness(
-  () => new FireSimTraceGenDUT)
-
-// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1
-class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)
-
-// Verilog blackbox integration demo
-class FireSimVerilogGCDDUT(implicit p: Parameters) extends FireSimDUT
-    with example.CanHavePeripheryGCD
-{
-  override lazy val module = new FireSimVerilogGCDModuleImp(this)
-}
-
-class FireSimVerilogGCDModuleImp[+L <: FireSimVerilogGCDDUT](l: L) extends FireSimModuleImp(l)
-
-class FireSimVerilogGCD(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimVerilogGCDDUT)

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -136,18 +136,18 @@ abstract class FireSimTestSuite(
   runSuite("verilator")(FastBlockdevTests)
 }
 
-class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config")
-class BoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
-class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimRocketChipConfig", "BaseF1Config") {
+class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "BaseF1Config")
+class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
+class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") {
   runSuite("verilator")(NICLoopbackTests)
 }
-class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")
-class RamModelBoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams")
+class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams")
+class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams")
 
 // Multiclock tests
 class RocketMulticlockF1Tests extends FireSimTestSuite(
-  "FireSimNoNIC",
-  "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig",
+  "FireSim",
+  "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig",
   "WithSynthAsserts_BaseF1Config")
 
 abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String)

generators/tracegen/src/main/scala/Configs.scala

@@ -60,19 +60,6 @@ class WithBoomTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
   case MaxHartIdBits => log2Ceil(params.size + up(TraceGenKey, site).length) max 1
 })
 
-
-class TraceGenConfig extends Config(
-  new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
-  new BaseConfig)
-
-class NonBlockingTraceGenConfig extends Config(
-  new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
-  new BaseConfig)
-
-class BoomTraceGenConfig extends Config(
-  new WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
-  new BaseConfig)
-
 class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
     extends Config((site, here, up) => {
   case TraceGenKey => params.map { dcp => TraceGenParams(
@@ -100,7 +87,3 @@ class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
   case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size)
 })
 
-class NonBlockingTraceGenL2Config extends Config(
-  new WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
-  new WithInclusiveCache ++
-  new BaseConfig)

generators/tracegen/src/main/scala/TestHarness.scala

@@ -1,27 +0,0 @@
-package tracegen
-
-import chisel3._
-import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.diplomacy.LazyModule
-import freechips.rocketchip.util.GeneratorApp
-
-class TestHarness(implicit p: Parameters) extends Module {
-  val io = IO(new Bundle {
-    val success = Output(Bool())
-  })
-
-  val dut = Module(LazyModule(new TraceGenSystem).module)
-  io.success := dut.success
-  dut.connectSimAXIMem()
-}
-
-object Generator extends GeneratorApp {
-  // specify the name that the generator outputs files as
-  override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
-
-  // generate files
-  generateFirrtl
-  generateAnno
-  generateTestSuiteMakefrags
-  generateArtefacts
-}

generators/utilities/src/main/resources/csrc/emulator.cc

@@ -35,6 +35,7 @@
 extern tsi_t* tsi;
 extern dtm_t* dtm;
 extern remote_bitbang_t * jtag;
+extern int dramsim;
 
 static uint64_t trace_count = 0;
 bool verbose;
@@ -124,6 +125,8 @@ int main(int argc, char** argv)
   char ** htif_argv = NULL;
   int verilog_plusargs_legal = 1;
 
+  dramsim = 0;
+
   while (1) {
     static struct option long_options[] = {
       {"cycle-count", no_argument,       0, 'c' },
@@ -132,6 +135,7 @@ int main(int argc, char** argv)
       {"seed",        required_argument, 0, 's' },
       {"rbb-port",    required_argument, 0, 'r' },
       {"verbose",     no_argument,       0, 'V' },
+      {"dramsim",     no_argument,       0, 'D' },
 #if VM_TRACE
       {"vcd",         required_argument, 0, 'v' },
       {"dump-start",  required_argument, 0, 'x' },
@@ -140,9 +144,9 @@ int main(int argc, char** argv)
     };
     int option_index = 0;
 #if VM_TRACE
-    int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:", long_options, &option_index);
+    int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:D", long_options, &option_index);
 #else
-    int c = getopt_long(argc, argv, "-chm:s:r:V", long_options, &option_index);
+    int c = getopt_long(argc, argv, "-chm:s:r:VD", long_options, &option_index);
 #endif
     if (c == -1) break;
  retry:
@@ -155,6 +159,7 @@ int main(int argc, char** argv)
       case 's': random_seed = atoi(optarg); break;
       case 'r': rbb_port = atoi(optarg);    break;
       case 'V': verbose = true;             break;
+      case 'D': dramsim = 1;                break;
 #if VM_TRACE
       case 'v': {
         vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w");
@@ -188,6 +193,8 @@ int main(int argc, char** argv)
 #endif
         else if (arg.substr(0, 12) == "+cycle-count")
           c = 'c';
+        else if (arg == "+dramsim")
+          c = 'D';
         // If we don't find a legacy '+' EMULATOR argument, it still could be
         // a VERILOG_PLUSARG and not an error.
         else if (verilog_plusargs_legal) {

generators/utilities/src/main/scala/Simulator.scala

@@ -83,6 +83,11 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
   }
   def resources(sim: Simulator): Seq[String] = Seq(
     "/testchipip/csrc/SimSerial.cc",
+    "/testchipip/csrc/SimDRAM.cc",
+    "/testchipip/csrc/mm.h",
+    "/testchipip/csrc/mm.cc",
+    "/testchipip/csrc/mm_dramsim2.h",
+    "/testchipip/csrc/mm_dramsim2.cc",
     "/csrc/SimDTM.cc",
     "/csrc/SimJTAG.cc",
     "/csrc/remote_bitbang.h",