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Author SHA1 Message Date
Hansung Kim
e9c206dfa2 Properly handle upstream and downstream backpressure for respQueues 2023-10-24 11:36:18 -07:00
Hansung Kim
8e0904a1ad Fix matchingSources logic when all lanes are invalid 
When all lanes are invalid so that arb.io.valid is 0, we should not
deassert d_ready.
 2023-10-23 22:10:10 -07:00
Hansung Kim
a14d8b6814 Properly handle TL dataWidth mismatch for core-to-sbus configs 
... using yet another TLWidthWidget
 2023-10-23 20:33:41 -07:00
Hansung Kim
2e37d2ce3f Only check opcode validity when fire 
... otherwise assertion goes off with garbage-value opcode during reset.
 2023-10-23 20:31:00 -07:00
Hansung Kim
0f9896e001 Instantiate coalescer inside VortexTile 
Currently runtime errors with unhandled D opcode inside coalescer.
 2023-10-23 15:01:37 -07:00
Hansung Kim
2091ef686b Rename defaultConfig -> DefaultCoalescerConfig 2023-10-23 14:50:15 -07:00
Hansung Kim
105bb37421 Make VortexCoreParams; bring VortexTile into rocketchip.tile 
Reduces duplicate declarations.  Need to properly split it out of
rocket-chip later.
 2023-10-23 13:04:48 -07:00
Hansung Kim
f4553ffdb1 Remove done TODO 2023-10-23 11:33:38 -07:00
Richard Yan
2a9f2f8421 fix typo 2023-10-19 17:10:56 -07:00
Richard Yan
77e3ad4934 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-10-19 16:16:24 -07:00
Richard Yan
9d8e9de8d0 differentiate addresses for different harts 2023-10-19 16:14:35 -07:00
Hansung Kim
805abd1b4b Bump vortex for TL port change 2023-10-18 20:05:55 -07:00
Hansung Kim
ff302c1ba5 Use VortexTLAdapter for useVxCache = true as well 2023-10-18 20:04:31 -07:00
Hansung Kim
0d92eb65d4 Increase sourceWidth to fix vx_wspawn sync bug 
With sourceWidth = 1, we hit an unsynchronized vx_wspawn bug, where the
previously spawned warps get killed and overridden by a new vx_wspawn
call before all the warps complete execution.  Setting sourceWidth = 1
somehow slows down the progress of the spawned warps in relation to warp
0 (presumably because fetch stalls, but not sure why they would slow
down more than warp 0) and results in this bug.   sourceWidth = 4 seems
to work for vecadd.
 2023-10-18 15:19:11 -07:00
Hansung Kim
fb97bd3c2b Decouple Vortex imem bundle from TL 2023-10-17 12:18:58 -07:00
Hansung Kim
e4dd0c21e9 Bump vortex 2023-10-16 20:45:18 -07:00
Hansung Kim
8ab0529354 Move VortexBundleA/D to Core; resolve TODOs 2023-10-16 17:54:12 -07:00
Hansung Kim
eb9772b750 Decouple Vortex dmem bundle from TL 
Previously VortexBundle was being instantiated using the parameters of
the TileLink bundle from VortexTile.  This results in tight coupling
between Vortex interface parameters and downstream TileLink parameters.
This change adds a standalone Bundle used by the VortexCore wrapper
and is independently instantiated from the TL params, i.e. different
source widths.  Ideally we want to move away from using TL-like
structures for VortexBundle and handling adapter logic completely
outside the core blackbox.
 2023-10-16 17:42:17 -07:00
Hansung Kim
db8625fb20 Simplify metadata type wrangling in SourceGen 2023-10-16 15:24:37 -07:00
Hansung Kim
154e61b1a3 Fix SourceGen metadata IO errors in coalescer 2023-10-16 11:43:20 -07:00
Hansung Kim
630d76461c Do proper TL sourceId allocation for Vortex dmem requests 
This fixes sourceId collision that occurs when naively re-using tag bit
of a Vortex dmem request as TL source, which happens because Vortex core
does not allocate a new LSU entry for writes.

`VortexSourceGen` module acts as a Vortax tag <-> new TL source ID
converter, where it allocates a new ID for every new Vortex request, and
restores its original tag bits from the metadata embedded in the
SourceGenerator module.

TODO:
- Decouple sourceWidth of downstream TL nodes from Vortex's tag bit
  width; they are set to be the same for convenience as of now
- Apply this to imem requests as well
 2023-10-16 01:19:55 -07:00
Hansung Kim
c34853447b Implement metadata retrieval in SourceGenerator 2023-10-16 01:11:50 -07:00
Hansung Kim
5b356b735c Fix unused warning in Coalescing 2023-10-15 23:24:32 -07:00
Hansung Kim
78012800e7 Clarify confusing in/outResp naming in SourceGenerator 2023-10-15 23:17:01 -07:00
Hansung Kim
cbd32b78a9 add metadata field in SourceGenerator table 
This enables using SourceGenerator as a sourceId converter/restorer.
 2023-10-15 22:56:07 -07:00
Hansung Kim
ff4fc66c56 Reformat 2023-10-15 13:36:55 -07:00
Richard Yan
dd194ca61d bump vortex 2023-10-13 15:25:49 -07:00
Richard Yan
8d479438b1 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-10-13 14:04:20 -07:00
Richard Yan
dfae96ec9d add wait register 2023-10-13 13:31:14 -07:00
Hansung Kim
b7a7a7a0a7 Bump vortex 2023-10-11 20:32:08 -07:00
Hansung Kim
dab1d907d6 Comment out hartid and fpu from VortexBundle 
These are mostly copied from Rocket and we're not sure they're necessary
for Vortex.
 2023-10-11 20:29:15 -07:00
Hansung Kim
acc66e413a Set Vortex CORE_ID parameter using Tile hartId 2023-10-11 20:28:04 -07:00
Hansung Kim
c368e92ddb Bump vortex 2023-10-06 21:31:22 -07:00
Hansung Kim
1de8a4ffa8 Update doc comments 2023-10-05 16:38:12 -07:00
Hansung Kim
e7a008ec74 Rename #define constants in SimMemTrace 
... to prevent collision with constants of the same name in other
verilog sources.
 2023-10-01 20:58:49 -07:00
Hansung Kim
5bf068306f Fix too large bitwidth error in Verilator 2023-10-01 20:57:46 -07:00
Hansung Kim
5ee4154f26 Fix C/verilog argument size mismatch on Verilator 2023-10-01 12:12:11 -07:00
joshua
a98ec2758e bump vortex 2023-09-29 00:52:23 -07:00
joshua
3566159c12 Merge remote-tracking branch 'origin/graphics' into vx_cache 2023-09-28 11:38:05 -07:00
Richard Yan
f0f395661d bump vortex 2023-09-27 10:53:38 -07:00
joshua
c403156127 fix merge errors (?) 2023-09-25 23:40:29 -07:00
Richard Yan
0f47ae078e add operand roms, bump vortex 2023-09-25 21:27:13 -07:00
joshua
c5bfb66ee5 it works 2023-09-24 17:43:00 -07:00
joshua
6a6f7fcaf0 still not working 2023-09-24 13:28:29 -07:00
joshua
63aee46908 still not sure what error is 2023-09-23 17:52:02 -07:00
joshua
e3f85da12c add vortex cache temporarily 2023-09-23 13:03:53 -07:00
Richard Yan
7c5281cd0e multilane support, args.bin ROM, verilog sources cleanup and vortex bump 2023-09-15 11:16:55 -07:00
Richard Yan
d392d76608 bump vortex and increase source ids 2023-09-11 14:06:08 -07:00
Richard Yan
43f95175f1 bump verilog sources, remove files and mem changes 2023-09-09 01:55:02 -07:00
Richard Yan
8cef2ae135 integrate vortex as tile 2023-09-08 14:25:37 -07:00