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9059d1e436ef8dc39936697fe2d175cf8045a2ae
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Author SHA1 Message Date
Hansung Kim
9059d1e436 Misc doc 2023-05-08 20:35:40 -07:00
Hansung Kim
fd0d09691b Create separate Configs for synthesizable dummy testbenches 2023-05-08 17:51:24 -07:00
Hansung Kim
f6be54a122 Set up proper Config system for numLanes 
TODO: tracefilename should not really be inside SIMTCoreParam.
 2023-05-08 17:34:29 -07:00
Vamber Yang
25c0b6cfa5 CoalArbiter RTL written, verification WIP, merged changes from graphics 2023-05-08 16:57:26 -07:00
Vamber Yang
9c2a55ae79 CoalArbiter RTL implementation first draft, verification WIP 2023-05-08 16:52:45 -07:00
Hansung Kim
3fae0b2c7a Use priority encoder for chooseLeaderIdx 2023-05-08 15:18:45 -07:00
Hansung Kim
2d4e28e862 Use WithoutTLMonitors to slightly speed up chiseltests 2023-05-08 14:38:15 -07:00
Hansung Kim
54a3e3cf72 Initiate memtrace DPI only when trace_read_ready 
This is required because otherwise we might overwrite into
the Verilog registers that contain a valid trace line that
was missed by downstream when it was not ready.  Basically
whenever trace_read_cycle stalls, we also want to stall
__in_* registers.
 2023-05-08 14:34:52 -07:00
Hansung Kim
2e219ea15a Connect CoalShiftQueue enq.ready to upstream TL.ready 
Now CoalShiftQueue can properly stall memtrace driver.
 2023-05-08 14:27:54 -07:00
Hansung Kim
8cdbc81bdd Only write in MemTraceLogger when TL fire 
Without this we log extraneous lines that were valid but not transacted with the
downstream as it was not ready, which affects validity of memtrace testing.
 2023-05-08 14:26:05 -07:00
Hansung Kim
6755cb3eec Lax traceReadCycle advancing logic 
Trying to advance trace cycle while downstream is blocking
is tricky because DPI call is synchronous, and that gives
timing difference between the line we have fired to downstream
and the current cycle counter we maintain.
Just stall the counter whenever downstream is not ready
for now.
 2023-05-08 00:49:30 -07:00
Hansung Kim
6b97b77572 Revert SimMemTrace.v to use posedge clock 
Doing function calls inside @(*) causes lint errors.  Instead, remove
staging registers to eliminate 1 cycle latency between DPI call and
when output is visible to Chisel.
 2023-05-08 00:14:48 -07:00
Vamber Yang
99d1e45a49 CoalArbiter RTL outgoing side implementation 2023-05-08 00:05:16 -07:00
Hansung Kim
f7df5045d4 Respect downstream TL A ready in MemTraceDriver 2023-05-07 23:55:54 -07:00
Hansung Kim
ba600db7e4 Backport SimMemTrace fix 2023-05-07 23:54:49 -07:00
Hansung Kim
737a760fcd Enable coverage tests for chiseltest 2023-05-07 22:58:20 -07:00
Hansung Kim
15889d7667 Take filename from Configs for easier trace testing 2023-05-07 19:09:25 -07:00
Hansung Kim
c75eaaf727 Backport SimMemTrace 2023-05-07 18:38:26 -07:00
Hansung Kim
a6dbfc3901 Fix config for unittest 2023-05-07 18:38:23 -07:00
Hansung Kim
5e073f2dec Doc update 2023-05-07 18:36:29 -07:00
Richard Yan
d2e56be157 update unit tests for new timing behavior & config 2023-05-07 14:35:53 -07:00
Richard Yan
262a20c992 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-05-07 02:34:11 -07:00
Richard Yan
86e7d3d60d numerous coalescer bug fixes + working unit test 2023-05-07 02:31:28 -07:00
Hansung Kim
2d4cd542c1 Backport SimMemTrace: non-chronological trace error 2023-05-06 23:21:08 -07:00
Hansung Kim
e64cb7a282 Backport SimMemTrace: enable parsing source, report errors 2023-05-06 23:13:45 -07:00
Hansung Kim
afd8a0910a Rename arbiter config and IO 2023-05-06 18:36:46 -07:00
Hansung Kim
caa5ebf943 Reformat MemTraceReader 2023-05-06 01:47:33 -07:00
Richard Yan
c783f147f9 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-05-05 23:02:28 -07:00
Richard Yan
457b67a8d4 coalReqT source width bug fix 2023-05-05 23:02:25 -07:00
Vamber Yang
124e974969 Merge remote-tracking branch 'origin/graphics' into local-dev-branch 2023-05-05 19:00:21 -07:00
Vamber Yang
3dad961082 define top level IO bundle for CoalArbiter 2023-05-05 19:00:01 -07:00
Hansung Kim
4ebcfbb9eb Revert deq.valid; force-set io.coalesceable instead for coal.enable 2023-05-05 15:51:59 -07:00
Hansung Kim
42b03edbf7 Update import path to cde to reflect upstream changes 2023-05-05 14:51:13 -07:00
Hansung Kim
bb6105a0c7 Add missing reset to CoalShiftQueue 
Fixes garbage data coming out of the queues in the first few cycles.
 2023-05-04 17:26:12 -07:00
Hansung Kim
aa0ce2998e Respect io.coalescable for deq.valid in CoalShiftQueue 
Otherwise disabling coalescer globally wouldn't work.
 2023-05-04 16:40:20 -07:00
Hansung Kim
1fa2e36740 Add global enable to coalescer config 2023-05-04 16:38:38 -07:00
Hansung Kim
eb802a2aaa Fix srcId config mismatch with MemTraceDriver 2023-05-04 15:41:06 -07:00
Hansung Kim
a1cdf10b20 Revert to non-synthesis TB; wip config compile error fix 2023-05-04 15:33:44 -07:00
Hansung Kim
888e4f091e Leftover synthesis dummy changes 2023-05-04 15:23:53 -07:00
Richard Yan
d4c2173f6e Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-05-03 17:59:20 -07:00
Richard Yan
ebd6c54d67 tl graph changes, coalescer bug fixes & coalescer unit test 2023-05-03 17:58:25 -07:00
Vamber Yang
84cc0334bb Get latest change from graphics before pushing 
Merge remote-tracking branch 'origin/graphics' into local-dev-branch
 2023-05-02 22:07:12 -07:00
Vamber Yang
8ccaf3864d Support for more realistic MemTracer step2 (DONE), make Verilog Blackbox DPI output data immediately and make .cc file maintain pointer when downstream is not ready 2023-05-02 22:06:16 -07:00
Richard Yan
736a8d4e98 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-05-02 17:40:08 -07:00
Richard Yan
459c14bb62 add testing infrastructure for coalescing unit 2023-05-02 17:38:49 -07:00
Vamber Yang
be0fcbd23b Support for more realistic MemTracer step 1, allow Chisel MemTracer to input read_cycle to Verilog blackbox 2023-05-02 14:01:19 -07:00
Richard Yan
b9953e43ca TL helper methods for entry types 2023-05-02 01:39:27 -07:00
Richard Yan
997b421c42 active byte lane implementation for multi coalescer & add one shift queue test 2023-05-02 00:07:45 -07:00
Richard Yan
6757ea1bbd shift queue bug fixes + new unit test 2023-05-01 00:51:31 -07:00
Richard Yan
224bc65bcc Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-04-30 17:59:16 -07:00