 Jerry Zhao
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4dd017d181
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Fix WithClockAndResetFromHarness to actually request harness clocks
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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f4bf1b0a28
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Fix multiclockrocketconfig
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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624785376a
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Fix PassThroughClockGenerator to handle multiclock properly
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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ffc4d1f662
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Use getClass.getSimpleName for ClockSourceAtFreqMHz blackbox inline
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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1916d3e4fc
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Add timeunit to ClockSourceAtFreqMHz
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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bcd273986f
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Fix ClockSourceAtFreqMHz period calc
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2023-05-11 15:04:03 -07:00 |
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Jerry Zhao
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5c8ea080ee
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Switch to our own ClockSourceAtFreq that is verilator-compatible
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2023-05-11 15:04:03 -07:00 |
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Jerry Zhao
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71fe1ad858
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Switch RTL sims to absolute clock-generators
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2023-05-11 15:04:03 -07:00 |
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Jerry Zhao
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c148f1daf1
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Make BootAddrReg optional
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2023-05-10 11:44:03 -07:00 |
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Jerry Zhao
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fbfb518b72
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Merge remote-tracking branch 'origin/main' into renameserial
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2023-05-10 11:39:11 -07:00 |
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Sagar KarandikarandGitHub
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1c10f75622
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Merge pull request #1471 from ucb-bar/lowmem-configs
Add 1GB / 4GB DRAM firechip configs for FireSim VCU118
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2023-05-10 11:32:01 -07:00 |
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Sagar Karandikar
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abe8a7fb8b
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remove extra newlines
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2023-05-10 11:31:05 -07:00 |
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Hansung Kim
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afbb67f934
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Bump rocket-chip
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2023-05-10 01:24:28 -07:00 |
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Hansung Kim
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013782a5db
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Update path to WithMemtraceCore
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2023-05-09 22:23:36 -07:00 |
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Jerry Zhao
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94f83e319a
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Fix bugs in spike-cosim
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2023-05-09 17:39:48 -07:00 |
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abejgonzalez
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2997cddc0e
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Merge remote-tracking branch 'origin/main' into bump-verilator
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2023-05-09 13:27:13 -07:00 |
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Hansung Kim
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58f3fc221c
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Bump rocket-chip to reflect memtrace config update
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2023-05-09 13:10:14 -07:00 |
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Hansung Kim
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87b64575f8
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Refactor memtrace SoC configuration
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2023-05-09 13:08:49 -07:00 |
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Jerry Zhao
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eced8e63d9
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Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness
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2023-05-08 18:19:18 -07:00 |
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Sagar Karandikar
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95da9cefb5
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4GB DRAM configs
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2023-05-08 13:41:51 -07:00 |
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Jerry Zhao
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ac281daa78
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Move TestHarness to chipyard.harness, make chipyard/harness directory
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2023-05-08 08:00:56 -07:00 |
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Jerry Zhao
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4f5bbdca97
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Flip serial_tl.clock for firechip BridgeBinders
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2023-05-07 22:22:37 -07:00 |
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Jerry Zhao
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9566667767
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Remove bus-to-bus crossings
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2023-05-07 22:22:37 -07:00 |
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Jerry Zhao
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5f076b184d
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Flip serial_tl_clock to be generated off-chip
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2023-05-07 22:22:36 -07:00 |
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Jerry Zhao
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4eb0f81c16
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Bump testchipip
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2023-05-07 16:02:23 -07:00 |
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Jerry Zhao
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954dab1638
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Merge remote-tracking branch 'origin/main' into tcdtm
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2023-05-07 15:56:55 -07:00 |
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Sagar Karandikar
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40d0a1f3bd
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low mem configs
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2023-05-07 11:47:14 -07:00 |
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Jerry Zhao
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2271194131
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Merge remote-tracking branch 'origin/main' into bump-fs
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2023-05-06 19:26:20 -07:00 |
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Jerry ZhaoandGitHub
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257e7d7507
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Check that HarnessClockInstantiator doesn't receive requests for similarly-named-clocks with different frequencies (#1460)
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2023-05-05 17:09:07 -07:00 |
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Hansung Kim
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774c9cb789
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Bump rocket-chip after upstream/master merge
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2023-05-05 14:51:36 -07:00 |
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Hansung Kim
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03350cfafe
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Update import path to cde to reflect upstream changes
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2023-05-05 14:47:45 -07:00 |
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Hansung Kim
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c9762296ca
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Merge remote-tracking branch 'upstream/main' into graphics
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2023-05-05 14:40:55 -07:00 |
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Jerry ZhaoandGitHub
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b8ccb7d4f6
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Support not instantiating the TileClockGater/ResetSetter PRCI controllers (#1459)
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2023-05-04 17:15:38 -07:00 |
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Jerry ZhaoandGitHub
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b05f36df79
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Fix support for no-bootROM systems (#1458)
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2023-05-03 18:23:36 -07:00 |
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Jerry ZhaoandGitHub
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1cc5ea5192
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Fix no-uart configs (#1457)
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2023-05-03 18:23:16 -07:00 |
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Jerry Zhao
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a299dae1a5
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Initialize cospike memory from SimDRAM memory
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2023-05-01 09:28:55 -07:00 |
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Hansung Kim
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9301243a03
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Bump rocket-chip
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2023-04-28 01:40:53 -07:00 |
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Tianrui Wei
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64e8f334ac
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fix: address comments
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
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2023-04-20 16:19:16 -07:00 |
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Tianrui Wei
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c5002ab9d3
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fix: address comments
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
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2023-04-20 16:10:40 -07:00 |
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Tianrui Wei
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91ccc7b25d
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feat: cospike changes
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
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2023-04-20 15:42:08 -07:00 |
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abejgonzalez
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2bf8f258ad
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Bump Gemmini
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2023-04-20 13:22:19 -07:00 |
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Jerry Zhao
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6701b85f27
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Bump testchipip
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2023-04-19 23:48:14 -07:00 |
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Jerry Zhao
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104a5299a9
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Fix typos
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2023-04-19 19:52:46 -07:00 |
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Jerry Zhao
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383a0fee96
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Bump testchipip to standardize tlserdes bundle params
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2023-04-19 11:44:20 -07:00 |
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Jerry Zhao
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2b3c5fc48e
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Merge remote-tracking branch 'origin/main' into tcdtm
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2023-04-17 18:14:43 -07:00 |
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Jerry Zhao
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4038217ae9
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Serial-TL backing memory configs should use 1 memory channel
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2023-04-17 17:56:44 -07:00 |
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Jerry Zhao
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c6bf50bc9d
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Update verilator's emulator.cc SIM_FILE_REQS
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2023-04-17 16:20:52 -07:00 |
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Jerry Zhao
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ad9ea333d1
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Bump TestChipIp to improve default serial_tl behavior
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2023-04-17 14:14:24 -07:00 |
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Jerry Zhao
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8c47f50a73
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Restore vector state as well for cosim loadarch
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2023-04-17 14:07:37 -07:00 |
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Jerry Zhao
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a7a441b6a8
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Bump testchipip
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2023-04-17 13:25:19 -07:00 |
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