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Serial-TL backing memory configs should use 1 memory channel

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This commit is contained in:
Jerry Zhao
2023-04-17 17:56:44 -07:00
parent c6bf50bc9d
commit 4038217ae9
2 changed files with 2 additions and 0 deletions
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generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -24,6 +24,7 @@ class ChipLikeQuadRocketConfig extends Config(
new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach fast SimDRAM to TestHarness
new chipyard.config.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
//==================================
// Set up clock./reset

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generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -125,6 +125,7 @@ class MulticlockAXIOverSerialConfig extends Config(
new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory
new freechips.rocketchip.subsystem.WithNBigCores(2) ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
new chipyard.config.AbstractConfig)
// DOC include end: MulticlockAXIOverSerialConfig