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Bump TestChipIp to improve default serial_tl behavior

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This commit is contained in:
Jerry Zhao
2023-04-10 15:35:53 -07:00
parent cf0db304a8
commit ad9ea333d1
2 changed files with 1 additions and 2 deletions
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1
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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@@ -39,7 +39,6 @@ class ChipLikeQuadRocketConfig extends Config(
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new testchipip.WithSerialTLAsyncResetQueue ++ // Add Async reset queue to block ready while in reset
new chipyard.config.AbstractConfig)

2
generators/testchipip

Submodule generators/testchipip updated: aa9170afe1...0d943d04b5