wu-arch/chipyard
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Fix typos

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This commit is contained in:
Jerry Zhao
2023-04-19 19:52:46 -07:00
parent cf87641031
commit 104a5299a9
4 changed files with 17 additions and 12 deletions
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2
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -185,7 +185,7 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBind
(system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
(ports zip system.memAXI4Node.edges.in).map { case (port, edge) =>
// TODO FIX: This currently makes each SimDRAM contian the entire memory space
// TODO FIX: This currently makes each SimDRAM contain the entire memory space
val memSize = p(ExtMem).get.master.size
val memBase = p(ExtMem).get.master.base
val lineSize = p(CacheBlockBytes)