Restore vector state as well for cosim loadarch
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@@ -189,7 +189,14 @@ extern "C" void cospike_cosim(long long int cycle,
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loadarch_state_t &ls = dtm->loadarch_state[hartid];
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s->pc = ls.pc;
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s->prv = ls.prv;
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s->csrmap[CSR_MSTATUS]->write(s->csrmap[CSR_MSTATUS]->read() | MSTATUS_VS | MSTATUS_XS | MSTATUS_FS);
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#define RESTORE(CSRID, csr) s->csrmap[CSRID]->write(ls.csr);
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RESTORE(CSR_FCSR , fcsr);
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RESTORE(CSR_VSTART , vstart);
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RESTORE(CSR_VXSAT , vxsat);
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RESTORE(CSR_VXRM , vxrm);
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RESTORE(CSR_VCSR , vcsr);
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RESTORE(CSR_VTYPE , vtype);
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RESTORE(CSR_STVEC , stvec);
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RESTORE(CSR_SSCRATCH , sscratch);
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RESTORE(CSR_SEPC , sepc);
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@@ -208,9 +215,18 @@ extern "C" void cospike_cosim(long long int cycle,
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RESTORE(CSR_MIP , mip);
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RESTORE(CSR_MCYCLE , mcycle);
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RESTORE(CSR_MINSTRET , minstret);
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if (ls.VLEN != p->VU.VLEN) {
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printf("VLEN mismatch loadarch: $d != spike: $d\n", ls.VLEN, p->VU.VLEN);
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abort();
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}
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if (ls.ELEN != p->VU.ELEN) {
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printf("ELEN mismatch loadarch: $d != spike: $d\n", ls.ELEN, p->VU.ELEN);
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abort();
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}
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for (size_t i = 0; i < 32; i++) {
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s->XPR.write(i, ls.XPR[i]);
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s->FPR.write(i, { (uint64_t)ls.FPR[i], (uint64_t)-1 });
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memcpy(p->VU.reg_file + i * ls.VLEN / 8, ls.VPR[i], ls.VLEN / 8);
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}
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spike_loadarch_done = true;
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p->clear_waiting_for_interrupt();
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