Move TestHarness to chipyard.harness, make chipyard/harness directory

generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala

@@ -15,7 +15,7 @@ import freechips.rocketchip.tile._
 import freechips.rocketchip.prci._
 
 import testchipip.{TLTileResetCtrl}
-import chipyard.{DefaultClockFrequencyKey}
+import chipyard.harness.{DefaultClockFrequencyKey}
 
 case class ChipyardPRCIControlParams(
   slaveWhere: TLBusWrapperLocation = CBUS,

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -8,8 +8,8 @@ class ChipLikeQuadRocketConfig extends Config(
   //==================================
   // Set up TestHarness
   //==================================
-  new chipyard.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness
-                                                           // NOTE: This only simulates properly in VCS
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness
+                                                                   // NOTE: This only simulates properly in VCS
 
   //==================================
   // Set up tiles

generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala

@@ -13,7 +13,7 @@ import freechips.rocketchip.tilelink.{HasTLBusParams}
 
 import chipyard._
 import chipyard.clocking._
-
+import chipyard.harness.{DefaultClockFrequencyKey}
 
 // The default RocketChip BaseSubsystem drives its diplomatic clock graph
 // with the implicit clocks of Subsystem. Don't do that, instead we extend

generators/chipyard/src/main/scala/example/CustomChipTop.scala

@@ -7,6 +7,7 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy.{InModuleBody}
 import barstools.iocell.chisel._
 import chipyard._
+import chipyard.harness.{BuildTop}
 
 // A "custom" IOCell with additional I/O
 // The IO don't do anything here in this example

generators/chipyard/src/main/scala/example/FlatTestHarness.scala

@@ -12,7 +12,7 @@ import freechips.rocketchip.subsystem.{CacheBlockBytes}
 import freechips.rocketchip.devices.debug.{SimJTAG}
 import freechips.rocketchip.jtag.{JTAGIO}
 import testchipip.{SerialTLKey, SerialAdapter, UARTAdapter, SimDRAM}
-import chipyard.{BuildTop}
+import chipyard.harness.{BuildTop}
 
 // A "flat" TestHarness that doesn't use IOBinders
 // use with caution.

generators/chipyard/src/main/scala/harness/HarnessClocks.scala

@@ -1,4 +1,4 @@
-package chipyard
+package chipyard.harness
 
 import chisel3._
 
@@ -8,10 +8,9 @@ import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import freechips.rocketchip.prci._
 
-import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
+import chipyard.harness.{ApplyHarnessBinders, HarnessBinders, HarnessClockInstantiatorKey}
 import chipyard.iobinders.HasIOBinders
 import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
-import chipyard.HarnessClockInstantiatorKey
 
 
 // HarnessClockInstantiators are classes which generate clocks that drive

generators/chipyard/src/main/scala/harness/TestHarness.scala

@@ -1,4 +1,4 @@
-package chipyard
+package chipyard.harness
 
 import chisel3._
 
@@ -11,6 +11,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkP
 import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
 import chipyard.iobinders.HasIOBinders
 import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
+import chipyard.{ChipTop}
 
 // -------------------------------
 // Chipyard Test Harness

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -30,7 +30,6 @@ import cva6.CVA6Tile
 import boom.common.{BoomTile}
 import barstools.iocell.chisel._
 import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey}
-import chipyard.{HasHarnessSignalReferences}
 import chipyard.harness._
 
 object MainMemoryConsts {