wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Refactor memtrace SoC configuration

Browse Source
This commit is contained in:
Hansung Kim
2023-05-09 13:08:49 -07:00
parent 774c9cb789
commit 87b64575f8
2 changed files with 7 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
generators/chipyard/src/main/scala/DigitalTop.scala
View File

@@ -27,7 +27,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
with freechips.rocketchip.tilelink.CanHaveGPUTracer // Enable GPU Tracer
with freechips.rocketchip.tilelink.CanHaveMemtraceCore // Enable memtrace core
with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim

17
generators/chipyard/src/main/scala/config/GPUConfig.scala
View File

@@ -3,20 +3,15 @@ package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
class GPUTracerConfig extends Config(
// Attaching GPU Tracer to SBus
new freechips.rocketchip.tilelink.WithGPUTracer(4, "vecadd.core1.thread4.trace")++
// Creating L2
class MemtraceCoreConfig extends Config(
// Memtrace core
new freechips.rocketchip.tilelink.WithMemtraceCore("vecadd.core1.thread4.trace")++
new freechips.rocketchip.subsystem.WithNLanes(4) ++
// L2
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(64) ++
// Small Rocket core that does nothing
new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
new chipyard.config.AbstractConfig
)