wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
4,613 Commits 2 Branches 0 Tags
eb6910aae00bcbad9b8f09fe40d0bc419fe42cbf
Commit Graph

4613 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Edward Wang
d48587b671 Update project-template for testchipip master 2018-11-02 12:05:36 -07:00
edwardcwang
74ca2bc491 Remove deprecated run-main 2018-10-31 13:47:28 -07:00
Albert Ou
cd82131748 verisim: Add verilator-harness.cc from testchipip/csrc 
This fixes #35 and matches firechip.

238afa543f
49b7982c82
 2018-10-05 09:24:35 -07:00
Albert Ou
048492e54c mk: Ensure that FIRRTL jar has updated timestamp 
SBT does not replace $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar if
compilation produces the same results.
 2018-10-02 17:43:51 -07:00
Albert Ou
220aeea4c8 Bump rocket-chip 
- Update Scala version to 2.12.4; work around SBT multi-project idiosyncrasies
- Remove HasSystemErrorSlave
 2018-09-29 13:30:07 -07:00
Howard Mao
a3684d01dd use build.sbt instead of jar files to collect packages 2018-05-03 17:09:59 -07:00
edwardcwang
93bf7895be Fix corner case in compiling a small mem using a large lib (#32) 
* Refactor bit pairs calculation into a separate function

* Minor clarifications

* Clarify MacroCompilerSpec helpers

* Add SmallTagArrayTest test

* Fix corner case in compiling a small mem using a large lib
 2018-04-26 10:33:55 -07:00
Howard Mao
4c8c6e29f0 update rocket-chip again 2018-04-18 17:13:07 -07:00
olix86
b599514934 Update Makefrag-verilator 
Changed verilator version from 3.904 to 3.920, which fixes a bug that prevented the default example to compile correctly
 2018-04-17 17:11:30 -07:00
Howard Mao
728251a922 fix bootrom race condition 2018-04-17 16:47:48 -07:00
Howard Mao
7dc738a831 DualCoreConfig should be actually dual core 2018-04-17 16:06:44 -07:00
Howard Mao
b8f369a4bd switch to rebased testchipip branch 2018-04-17 15:56:22 -07:00
Howard Mao
7e70e3525f move bootrom to testchipip 2018-04-17 15:13:47 -07:00
Howard Mao
f1a55d531e bump rocket-chip to April commit 2018-04-17 11:59:45 -07:00
Howard Mao
28539dc562 bump rocket-chip to March commit 2018-04-16 19:33:51 -07:00
edwardcwang
f7634b82cd Include macro compiler JAR compilation instructions 2018-03-21 14:50:18 -07:00
Howard Mao
d88c2fa84f add regression tests to makefile 2018-02-23 13:48:45 -08:00
Howard Mao
073c16961e make sure annotations are generated and carried through to verilog elaboration 2018-02-23 11:50:33 -08:00
Howard Mao
1dfe9b1c9f bump rocket-chip and fix deprecated code in testchipip.GeneratorApp 2018-02-23 11:46:40 -08:00
Howard Mao
eaff48e312 fix issue #20: PWMConfig elaboration error due to requirement failure 2018-02-23 10:54:05 -08:00
Howard Mao
e3f05011c1 bugfix for verilator test harness 2018-02-23 10:35:01 -08:00
Edward Wang
1ccd8f6dbc Bump mdf to match master 2018-02-16 16:03:08 -08:00
Adam Izraelevitz
79c8c283cc Add memory compiler to macros (#29) 
* Add memory compiler to macros

* Removed weird spacing

* Make sramcompiler width/depth range inclusive

* Added sramcompiler test
 2018-02-16 16:01:10 -08:00
Howard Mao
080fdb835e fix testchipip SimSerial csrc for new htif_t constructor 2018-01-29 10:44:16 -08:00
Donggyu Kim
ed13397967 changes for new rocket-chip 2018-01-15 16:07:44 -08:00
edwardcwang
8a30579a3e Support firrtl output in command line for MacroCompiler (#28) 
* Use the given port prefix (fix a bug preventing two unit tests from passing)
* Support firrtl output in addition to Verilog
 2017-12-04 15:12:42 -08:00
Howard Mao
269660bbfe take pingd and nic-loopback out of Makefile 2017-11-30 20:50:01 -08:00
Howard Mao
e4a4046375 get RV32 working 2017-11-03 18:00:27 -07:00
Howard Mao
52068497c4 changes to block device memory map 2017-10-26 13:27:20 -07:00
Howard Mao
2223932bd2 disable compressed instructions in bootrom 2017-10-26 13:26:57 -07:00
Howard Mao
5c200ddb6e bump rocket-chip and testchipip 2017-10-26 13:20:13 -07:00
edwardcwang
c884a2fb15 Correct multi-ported memory compilation (#27) 
* Correct multi-ported memory compilation

It was incorrectly splitting multiple times before. Fixed the issue and
added regression tests for this issue.

* Add 1 read 1 write test
 2017-10-06 18:04:49 -07:00
Edward Wang
e1499fcdc0 Update command line help 2017-10-03 11:56:30 -07:00
Edward Wang
c91d98d5b3 Bump mdf for the last time, for now 2017-10-03 11:56:30 -07:00
Edward Wang
e09f8b1b0d Fix grammar 2017-10-03 11:56:30 -07:00
Edward Wang
bc26f5eb1a Address review comments 2017-10-03 11:56:30 -07:00
Edward Wang
d2b105079d Not a scaladoc 2017-10-03 11:56:30 -07:00
Edward Wang
4eca53ba55 Bump mdf again 2017-10-03 11:56:30 -07:00
Edward Wang
13d8a0f8f5 Add strict mode 2017-10-03 11:56:30 -07:00
Edward Wang
11bd81165b Bump mdf 2017-10-03 11:56:30 -07:00
Edward Wang
43d242707b Enable some more tests 2017-10-03 11:56:30 -07:00
Edward Wang
af67540a81 Add test from Donggyu 2017-10-03 11:56:30 -07:00
Edward Wang
5d3bebd2b9 Re-implement parallel mapping 
- Support byte-masked SRAM, yay
- Also nuke a bunch of bugs
 2017-10-03 11:56:30 -07:00
Edward Wang
676b8e72ba Add rocket-chip inspired tests 2017-10-03 11:56:30 -07:00
Edward Wang
e726daec41 Bump mdf 2017-10-03 11:56:30 -07:00
Edward Wang
e89079f2d7 Test for non-empty Verilog 2017-10-03 11:56:30 -07:00
Edward Wang
f9edbfea27 Move cost metric to its own file 2017-10-03 11:56:30 -07:00
Edward Wang
df8b5815c6 Trim redundant MDF field 2017-10-03 11:56:30 -07:00
Edward Wang
4013b1924f Implement command line cost metric selection 2017-10-03 11:56:30 -07:00
Edward Wang
0f4683700f Add cost function selection test 2017-10-03 11:56:30 -07:00