edwardcwang 8a30579a3e Support firrtl output in command line for MacroCompiler (#28)
* Use the given port prefix (fix a bug preventing two unit tests from passing)
* Support firrtl output in addition to Verilog
2017-12-04 15:12:42 -08:00
2017-10-03 11:56:30 -07:00
2017-10-03 11:56:30 -07:00
2017-03-05 18:50:56 -08:00
2017-10-03 11:56:30 -07:00
2017-02-17 11:58:05 -08:00
2017-02-17 11:58:05 -08:00
2017-02-17 11:58:05 -08:00

barstools

Useful utilities for BAR projects

Passes/Transforms that could be useful if added here:

  • Check that a module was de-duplicated. Useful for MIM CAD flows and currently done in python.

Be sure to publish-local the following repositories:

  • ucb-bar/chisel-testers (requires ucb-bar/firrtl-interpreter)
  • ucb-bar/firrtl

Example Usage:

sbt
> compile
> project tapeout
> run-main barstools.tapeout.transforms.GenerateTop -i <myfile>.fir -o <myfile>.v --syn-top <mysyntop> --harness-top <myharnesstop>
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