Zitao Fang
|
0995f1b04b
|
UCode passed all tests
|
2020-09-02 21:25:36 -07:00 |
|
Jerry Zhao
|
4b30462320
|
Change default IO set to JTAG+Serial, instead of JTAG+DMI
|
2020-09-02 20:19:27 -07:00 |
|
Zitao Fang
|
bb1d0a10ae
|
Stage 3 (single port) passed all tests
|
2020-08-31 18:00:40 -07:00 |
|
Jerry Zhao
|
c8448cc3e1
|
Bore out a bus clock to drive DebugIO from ChipTop
|
2020-08-30 18:10:52 -07:00 |
|
Zitao Fang
|
5c5af7bfad
|
Stage 3 passed all tests
|
2020-08-28 18:37:47 -07:00 |
|
Jerry Zhao
|
17239c56f8
|
Update AddIOCells.debug comment
|
2020-08-28 14:36:09 -07:00 |
|
Jerry Zhao
|
27b78f4de2
|
Only punch realistic subset of DebugIO through chiptop
|
2020-08-28 14:30:59 -07:00 |
|
Jerry Zhao
|
ee1ce1141c
|
Merge pull request #614 from ucb-bar/diplomatic-clocks
Diplomatic multiclock
|
2020-08-27 21:09:54 -07:00 |
|
Jerry Zhao
|
239b6b6e09
|
Bump testchipip
|
2020-08-27 13:00:43 -07:00 |
|
Jerry Zhao
|
e275a45890
|
Address PR comments
|
2020-08-26 12:34:46 -07:00 |
|
abejgonzalez
|
2168813da0
|
Add help string | Fix emulator CC to not conflict with --vpi
|
2020-08-21 14:07:32 -07:00 |
|
abejgonzalez
|
c9791ccbdf
|
Update docs | Revert/Update emulator.cc
|
2020-08-21 12:06:18 -07:00 |
|
abejgonzalez
|
425b8ce850
|
Add support for multi-threaded verilator
|
2020-08-20 23:37:17 -07:00 |
|
Zitao Fang
|
b0b09870dd
|
2-stage core passed all tests
|
2020-08-17 21:11:44 -07:00 |
|
Zitao Fang
|
84359abd19
|
Isolated master adapter's TileLink valid signals from the core
|
2020-08-16 16:07:38 -07:00 |
|
Zitao Fang
|
97f595f415
|
1-stage passed all tests
|
2020-08-16 15:41:44 -07:00 |
|
Zitao Fang
|
f6992c61c8
|
5-stage CPU passed all tests
|
2020-08-15 00:20:47 -07:00 |
|
Zitao Fang
|
03e50178f1
|
Add misalignment detection & make M-extension test optional
|
2020-08-14 16:00:38 -07:00 |
|
Zitao Fang
|
90a7caa323
|
Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
|
2020-08-12 14:27:08 -07:00 |
|
Zitao Fang
|
751215dec1
|
5-stage core running
|
2020-08-12 14:26:49 -07:00 |
|
Jerry Zhao
|
abc75e9b95
|
Fix Reset bug
|
2020-08-07 17:50:23 -07:00 |
|
Zitao Fang
|
7f5b324d06
|
Added interrupt
|
2020-08-05 17:16:36 -07:00 |
|
Jerry Zhao
|
9e443130b9
|
Merge remote-tracking branch 'origin/dev' into diplomatic-clocks
|
2020-08-05 14:21:16 -07:00 |
|
Colin Schmidt
|
5bfc289677
|
Bump fesvr for better loadmem impl. Fix verilator loadmem support
|
2020-08-05 10:05:02 -07:00 |
|
Howard Mao
|
09cc1bb985
|
Merge pull request #635 from ucb-bar/loadmem
Implement fast loadmem feature
|
2020-08-04 15:39:45 -07:00 |
|
Jerry Zhao
|
578ae6fca2
|
Bump to July 2020 rocketchip
|
2020-08-04 14:00:02 -07:00 |
|
Jerry Zhao
|
c7586be0c5
|
Merge pull request #629 from ucb-bar/random-seed
Add RANDOM_SEED variable to set random init for VCS and Verilator simulations
|
2020-08-03 14:46:16 -07:00 |
|
Howard Mao
|
d7f3f91f18
|
implement fast loadmem feature
|
2020-08-01 15:04:18 -07:00 |
|
Zitao Fang
|
a2bd26b91c
|
Finished Sodor Design
|
2020-07-31 20:54:42 -07:00 |
|
Zitao Fang
|
98ef89cbde
|
Created Internal Tiles
|
2020-07-29 15:02:33 -07:00 |
|
Zitao Fang
|
6131ab58e5
|
Connect cores
|
2020-07-28 13:37:07 -07:00 |
|
Zitao Fang
|
14e2a9dbd1
|
Fixed tile_master
|
2020-07-24 14:17:29 -07:00 |
|
Zitao Fang
|
d56df6252c
|
Sync
|
2020-07-23 19:24:44 -07:00 |
|
Jerry Zhao
|
fdfef878af
|
Merge branch 'dev' into diplomatic-clocks
|
2020-07-21 11:21:51 -07:00 |
|
Jerry Zhao
|
b719919934
|
Add RANDOM_SEED variable to set random init for VCS and Verilator simulations
|
2020-07-20 18:25:18 -07:00 |
|
Zitao Fang
|
fddf218147
|
5th revision
|
2020-07-16 15:39:07 -07:00 |
|
Zitao Fang
|
7bb1a48b1a
|
Connect TileLink nodes
|
2020-07-16 14:12:29 -07:00 |
|
Zitao Fang
|
97b8c3035c
|
Merge branch 'dev' of github.com:ucb-bar/chipyard into custom-core-doc
|
2020-07-15 11:15:46 -07:00 |
|
Zitao Fang
|
7ea464dc90
|
4th revision
|
2020-07-14 12:49:36 -07:00 |
|
Zitao Fang
|
1933fd8cbe
|
Update sodor package structure
|
2020-07-14 12:10:12 -07:00 |
|
Zitao Fang
|
ced7ea634c
|
3rd Revision
|
2020-07-12 01:08:13 -07:00 |
|
David Biancolin
|
d5a2d43f85
|
Merge pull request #612 from ucb-bar/zynq-target
[firechip] Add a small target that should fit on all hosts
|
2020-07-10 18:12:34 -07:00 |
|
Albert Ou
|
fbc71d4215
|
Merge pull request #625 from ucb-bar/uart
Override default baud rate for FireChip
|
2020-07-10 10:55:50 -07:00 |
|
Jerry Zhao
|
7239e23185
|
Merge branch 'dev' into simple_configs
|
2020-07-09 11:31:33 -07:00 |
|
Jerry Zhao
|
11c87777fe
|
Remove BOOM debug print
|
2020-07-09 11:29:58 -07:00 |
|
Zitao Fang
|
9ad9d00a23
|
Second revision
|
2020-07-08 16:02:31 -07:00 |
|
Zitao Fang
|
85069387c9
|
Base Scratchpad
|
2020-07-08 14:45:12 -07:00 |
|
Albert Ou
|
763ba42b4c
|
Bump testchipip for FDT alignment and minLatency fixes
|
2020-07-08 12:36:09 -07:00 |
|
Albert Ou
|
b55e579c91
|
Override default baud rate for FireChip
This avoids target software needing to explicitly set the divisor to
match the UART bridge.
|
2020-07-07 23:00:14 -07:00 |
|
Jerry Zhao
|
56e1aeb400
|
Support FireSim diplomatic multiclock
|
2020-07-07 20:54:31 -07:00 |
|