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Bump to July 2020 rocketchip

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This commit is contained in:
Jerry Zhao
2020-08-03 14:23:08 -07:00
parent fdfef878af
commit 578ae6fca2
19 changed files with 142 additions and 119 deletions
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2
.circleci/do-rtl-build.sh
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@@ -59,7 +59,7 @@ run "export RISCV=\"$TOOLS_DIR\"; \
export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
make -C $REMOTE_SIM_DIR clean; \
make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}"
make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}"
run "rm -rf $REMOTE_CHIPYARD_DIR/project"
# copy back the final build

2
generators/ariane

Submodule generators/ariane updated: 0ed9107485...3a2eed602f

2
generators/boom

Submodule generators/boom updated: 859c60553b...dc22cacf71

17
generators/chipyard/src/main/scala/ChipTop.scala
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@@ -32,10 +32,8 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc
// The system module specified by BuildSystem
val lSystem = LazyModule(p(BuildSystem)(p)).suggestName("system")
// The systemClockSinkNode provides the implicit clock and reset for the System
val systemClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters()))
val systemClockGroup = LazyModule(new ClockGroup("system_clock"))
systemClockSinkNode := systemClockGroup.node
// The implicitClockSinkNode provides the implicit clock and reset for the System
val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters()))
// Generate Clocks and Reset
p(ChipyardClockKey)(this)
@@ -46,12 +44,13 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc
// anyways, they probably need to be explicitly clocked.
lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) {
// These become the implicit clock and reset to the System
val system_clock = systemClockSinkNode.in.head._1.clock
val system_reset = systemClockSinkNode.in.head._1.reset
val implicit_clock = implicitClockSinkNode.in.head._1.clock
val implicit_reset = implicitClockSinkNode.in.head._1.reset
// The implicit clock and reset for the system is also, by convention, used for all the IOBinders
// TODO: This may not be the right thing to do in all cases
withClockAndReset(system_clock, system_reset) {
withClockAndReset(implicit_clock, implicit_reset) {
val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(lSystem.module)).unzip3
// We ignore _ports for now...
iocells ++= _iocells.flatten
@@ -60,8 +59,8 @@ class ChipTop(implicit p: Parameters) extends LazyModule with HasTestHarnessFunc
// Connect the implicit clock/reset, if present
lSystem.module match { case l: LazyModuleImp => {
l.clock := system_clock
l.reset := system_reset
l.clock := implicit_clock
l.reset := implicit_reset
}}
}
}

77
generators/chipyard/src/main/scala/Clocks.scala
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@@ -83,59 +83,65 @@ case object ChipyardClockKey extends Field[ChipTop => Unit](ClockDrivers.harness
object ClockDrivers {
// A simple clock provider, for testing. All clocks in system are aggregated into one,
// and are driven by directly punching out to the TestHarness clock
// A simple clock provider, for testing
val harnessClock: ChipTop => Unit = { chiptop =>
implicit val p = chiptop.p
val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
val clockAggregator = LazyModule(new ClockGroupAggregator("clocks"))
// Aggregate all 3 possible clock groups with the clockAggregator
chiptop.systemClockGroup.node := clockAggregator.node
if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) {
chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := clockAggregator.node }
}
chiptop.lSystem match {
case l: ChipyardSubsystem => l.tileClockGroupNode := clockAggregator.node
case _ =>
val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters()))
chiptop.implicitClockSinkNode := implicitClockSourceNode
// Drive the diplomaticclock graph of the DigitalTop (if present)
val simpleClockGroupSourceNode = chiptop.lSystem match {
case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => {
val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
l.asyncClockGroupsNode := n
Some(n)
}
case _ => None
}
clockAggregator.node := simpleClockGroupSourceNode
InModuleBody {
// this needs directionality so generateIOFromSignal works
//this needs directionality so generateIOFromSignal works
val clock_wire = Wire(Input(Clock()))
val reset_wire = GenerateReset(chiptop, clock_wire)
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock"))
chiptop.iocells ++= clockIOCell
clock_io.suggestName("clock")
simpleClockGroupSourceNode.out.unzip._1.flatMap(_.member).map { o =>
implicitClockSourceNode.out.unzip._1.map { o =>
o.clock := clock_wire
o.reset := reset_wire
}
simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock_wire
o.reset := reset_wire
}
}}
chiptop.harnessFunctions += ((th: HasHarnessUtils) => {
clock_io := th.harnessClock
Nil
})
}
}
val harnessMultiClock: ChipTop => Unit = { chiptop =>
val harnessDividedClock: ChipTop => Unit = { chiptop =>
implicit val p = chiptop.p
val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters(), ClockGroupSourceParameters()))
val uncoreClockAggregator = LazyModule(new ClockGroupAggregator("uncore_clocks"))
// Aggregate only the uncoreclocks
chiptop.systemClockGroup.node := uncoreClockAggregator.node
if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) {
chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := uncoreClockAggregator.node }
}
val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters()))
chiptop.implicitClockSinkNode := implicitClockSourceNode
uncoreClockAggregator.node := simpleClockGroupSourceNode
chiptop.lSystem match {
case l: ChipyardSubsystem => l.tileClockGroupNode := simpleClockGroupSourceNode
case _ => throw new Exception("MultiClock assumes ChipyardSystem")
val simpleClockGroupSourceNode = chiptop.lSystem match {
case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => {
val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
l.asyncClockGroupsNode := n
Some(n)
}
case _ => throw new Exception("Harness multiclock assumes BaseSubsystem")
}
InModuleBody {
@@ -147,14 +153,19 @@ object ClockDrivers {
clock_io.suggestName("clock")
val div_clock = Pow2ClockDivider(clock_wire, 2)
simpleClockGroupSourceNode.out(0)._1.member.map { o =>
implicitClockSourceNode.out.unzip._1.map { o =>
o.clock := div_clock
o.reset := ResetCatchAndSync(div_clock, reset_wire.asBool)
}
simpleClockGroupSourceNode.out(1)._1.member.map { o =>
o.clock := clock_wire
o.reset := reset_wire
}
simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle =>
out.member.elements.map { case (name, data) =>
// This is mega hacks, how are you actually supposed to do this?
data.clock := (if (name.contains("core")) clock_wire else div_clock)
data.reset := reset_wire
}
}}
chiptop.harnessFunctions += ((th: HasHarnessUtils) => {
clock_io := th.harnessClock
Nil

10
generators/chipyard/src/main/scala/ConfigFragments.scala
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@@ -6,12 +6,13 @@ import chisel3.util.{log2Up}
import freechips.rocketchip.config.{Field, Parameters, Config}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy.{LazyModule, ValName}
import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.devices.tilelink.{BootROMLocated}
import freechips.rocketchip.devices.debug.{Debug}
import freechips.rocketchip.groundtest.{GroundTestSubsystem}
import freechips.rocketchip.tile._
import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
import freechips.rocketchip.util.{AsyncResetReg}
import freechips.rocketchip.prci._
import testchipip._
import tracegen.{TraceGenSystem}
@@ -33,8 +34,7 @@ import chipyard.{BuildTop, BuildSystem, ClockDrivers, ChipyardClockKey, TestSuit
// -----------------------
class WithBootROM extends Config((site, here, up) => {
case BootROMParams => BootROMParams(
contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img"))
})
// DOC include start: gpio config fragment
@@ -159,6 +159,6 @@ class WithNoSubsystemDrivenClocks extends Config((site, here, up) => {
case SubsystemDriveAsyncClockGroupsKey => None
})
class WithTileMultiClock extends Config((site, here, up) => {
case ChipyardClockKey => ClockDrivers.harnessMultiClock
class WithTileDividedClock extends Config((site, here, up) => {
case ChipyardClockKey => ClockDrivers.harnessDividedClock
})

18
generators/chipyard/src/main/scala/Subsystem.scala
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@@ -35,32 +35,16 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
case b: BoomTile => b.module.core.coreMonitorBundle
}.toList
val tileClockSinkNode = ClockSinkNode(List(ClockSinkParameters()))
val tileClockGroup = LazyModule(new ClockGroup("tile_clock"))
val tileClockGroupNode = tileClockGroup.node
tileClockSinkNode := tileClockGroupNode
override lazy val module = new ChipyardSubsystemModuleImp(this)
}
class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasResetVectorWire
with HasTilesModuleImp
{
for (i <- 0 until outer.tiles.size) {
val wire = tile_inputs(i)
wire.hartid := outer.hartIdList(i).U
wire.reset_vector := global_reset_vector
outer.tiles(i).module.clock := outer.tileClockSinkNode.in.head._1.clock
outer.tiles(i).module.reset := outer.tileClockSinkNode.in.head._1.reset
}
// create file with core params
ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
// Generate C header with relevant information for Dromajo
// This is included in the `dromajo_params.h` header file
DromajoHelper.addArtefacts()
DromajoHelper.addArtefacts(InSubsystem)
}

5
generators/chipyard/src/main/scala/System.scala
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@@ -26,8 +26,10 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
with CanHaveMasterAXI4MemPort
with CanHaveMasterAXI4MMIOPort
with CanHaveSlaveAXI4Port
with HasPeripheryBootROM
{
val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
override lazy val module = new ChipyardSystemModule(this)
}
@@ -37,5 +39,4 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer)
with HasRTCModuleImp
with HasExtInterruptsModuleImp
with HasPeripheryBootROMModuleImp
with DontTouch

2
generators/chipyard/src/main/scala/TestHarness.scala
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@@ -28,7 +28,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessUtil
val success = Output(Bool())
})
val ldut = LazyModule(p(BuildTop)(p)).suggestName("ChipTop")
val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
val dut = Module(ldut.module)
io.success := false.B

11
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -187,8 +187,15 @@ class MMIORocketConfig extends Config(
// NOTE: This config doesn't work yet because SimWidgets in the TestHarness
// always get the TestHarness clock. The Tiles and Uncore receive the correct clocks
class MultiClockRocketConfig extends Config(
new chipyard.config.WithTileMultiClock ++ // Put the Tile on its own clock domain
class DividedClockRocketConfig extends Config(
new chipyard.config.WithTileDividedClock ++ // Put the Tile on its own clock domain
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class TestClockRocketConfig extends Config(
//new chipyard.config.WithTileMultiClock ++ // Put the Tile on its own clock domain
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(8, 3) ++ // Add rational crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

71
generators/firechip/src/main/scala/FireSim.scala
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@@ -45,26 +45,36 @@ object NodeIdx {
class WithFireSimSimpleClocks extends Config((site, here, up) => {
case ChipyardClockKey => { chiptop: ChipTop =>
implicit val p = chiptop.p
val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
val clockAggregator = LazyModule(new ClockGroupAggregator("clocks"))
// Aggregate all 3 possible clock groups with the clockAggregator
chiptop.systemClockGroup.node := clockAggregator.node
if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) {
chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := clockAggregator.node }
val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters()))
chiptop.implicitClockSinkNode := implicitClockSourceNode
// Drive the diplomaticclock graph of the DigitalTop (if present)
val simpleClockGroupSourceNode = chiptop.lSystem match {
case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => {
val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
l.asyncClockGroupsNode := n
Some(n)
}
case _ => None
}
chiptop.lSystem match { case l: ChipyardSubsystem => l.tileClockGroupNode := clockAggregator.node }
clockAggregator.node := simpleClockGroupSourceNode
InModuleBody {
val clock = IO(Input(Clock())).suggestName("clock")
val reset = IO(Input(Reset())).suggestName("reset")
val clock = IO(Input(Clock())).suggestName("clock")
val reset = IO(Input(Reset())).suggestName("reset")
simpleClockGroupSourceNode.out.unzip._1.flatMap(_.member).map { o =>
implicitClockSourceNode.out.unzip._1.map { o =>
o.clock := clock
o.reset := reset
}
simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock
o.reset := reset
}
}}
chiptop.harnessFunctions += ((th: HasHarnessUtils) => {
clock := th.harnessClock
reset := th.harnessReset
@@ -78,19 +88,18 @@ class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Confi
case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor)))
case ChipyardClockKey => { chiptop: ChipTop =>
implicit val p = chiptop.p
val simpleClockGroupSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters(), ClockGroupSourceParameters()))
val uncoreClockAggregator = LazyModule(new ClockGroupAggregator("uncore_clocks"))
// Aggregate only the uncoreclocks
chiptop.systemClockGroup.node := uncoreClockAggregator.node
if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) {
chiptop.lSystem match { case l: BaseSubsystem => l.asyncClockGroupsNode := uncoreClockAggregator.node }
}
val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters()))
chiptop.implicitClockSinkNode := implicitClockSourceNode
uncoreClockAggregator.node := simpleClockGroupSourceNode
chiptop.lSystem match {
case l: ChipyardSubsystem => l.tileClockGroupNode := simpleClockGroupSourceNode
case _ => throw new Exception("MultiClock assumes ChipyardSystem")
// Drive the diplomaticclock graph of the DigitalTop (if present)
val simpleClockGroupSourceNode = chiptop.lSystem match {
case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => {
val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
l.asyncClockGroupsNode := n
Some(n)
}
case _ => None
}
InModuleBody {
@@ -98,15 +107,23 @@ class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Confi
val tile_clock = IO(Input(Clock())).suggestName("tile_clock")
val reset = IO(Input(Reset())).suggestName("reset")
simpleClockGroupSourceNode.out(0)._1.member.map { o =>
implicitClockSourceNode.out.unzip._1.map { o =>
o.clock := uncore_clock
o.reset := reset
}
simpleClockGroupSourceNode.out(1)._1.member.map { o =>
o.clock := tile_clock
o.reset := ResetCatchAndSync(tile_clock, reset.asBool)
}
simpleClockGroupSourceNode.map { n => n.out.unzip._1.map { out: ClockGroupBundle =>
out.member.elements.map { case (name, data) =>
// This is mega hacks, how are you actually supposed to do this?
if (name.contains("core")) {
data.clock := tile_clock
data.reset := ResetCatchAndSync(tile_clock, reset.asBool)
} else {
data.clock := uncore_clock
data.clock := reset
}
}
}}
chiptop.harnessFunctions += ((th: HasHarnessUtils) => {
uncore_clock := th.harnessClock

14
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -10,7 +10,7 @@ import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.rocket.DCacheParams
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
import freechips.rocketchip.diplomacy.LazyModule
import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams}
@@ -24,16 +24,16 @@ import firesim.bridges._
import firesim.configs._
class WithBootROM extends Config((site, here, up) => {
case BootROMParams => {
case BootROMLocated(x) => {
val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img")
val firesimBootROM = new File(s"./target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img")
val bootROMPath = if (chipyardBootROM.exists()) {
val bootROMPath = if (chipyardBootROM.exists()) {
chipyardBootROM.getAbsolutePath()
} else {
firesimBootROM.getAbsolutePath()
}
BootROMParams(contentFileName = bootROMPath)
up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMPath))
}
})
@@ -188,11 +188,13 @@ class FireSimArianeConfig extends Config(
new WithFireSimConfigTweaks ++
new chipyard.ArianeConfig)
//**********************************************************************************
//* Multiclock Configurations
//*********************************************************************************/
class FireSimMulticlockRocketConfig extends Config(
new WithFireSimRationalTileDomain(2, 1) ++
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.MultiClockRocketConfig)
new chipyard.DividedClockRocketConfig)

2
generators/hwacha

Submodule generators/hwacha updated: a989b69759...e29b65db86

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 653efa99a2...6eb1a3de08

2
generators/testchipip

Submodule generators/testchipip updated: 8b5c89a5f7...3bfd710ce3

10
generators/tracegen/src/main/scala/System.scala
View File

@@ -12,6 +12,10 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
with CanHaveMasterAXI4MemPort {
def coreMonitorBundles = Nil
val tileStatusNodes = tiles.collect {
case t: GroundTestTile => t.statusNode.makeSink()
case t: BoomTraceGenTile => t.statusNode.makeSink()
}
override lazy val module = new TraceGenSystemModuleImp(this)
}
@@ -20,12 +24,8 @@ class TraceGenSystemModuleImp(outer: TraceGenSystem)
{
val success = IO(Output(Bool()))
outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := i.U }
val status = dontTouch(DebugCombiner(outer.tileStatusNodes.map(_.bundle)))
val status = dontTouch(DebugCombiner(outer.tiles.collect {
case t: GroundTestTile => t.module.status
case t: BoomTraceGenTile => t.module.status
}))
success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR
}

10
generators/tracegen/src/main/scala/Tile.scala
View File

@@ -3,7 +3,7 @@ package tracegen
import chisel3._
import chisel3.util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, SynchronousCrossing, ClockCrossingType}
import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, SynchronousCrossing, ClockCrossingType, BundleBridgeSource}
import freechips.rocketchip.groundtest._
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.constants.{MemoryOpConstants}
@@ -206,11 +206,13 @@ class BoomTraceGenTile private(
val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil)
val intOutwardNode: IntOutwardNode = IntIdentityNode()
val slaveNode: TLInwardNode = TLIdentityNode()
val statusNode = BundleBridgeSource(() => new GroundTestStatus)
val boom_params = p.alterMap(Map(TileKey -> BoomTileParams(
dcache=params.dcache,
core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false))))
val dcache = LazyModule(new BoomNonBlockingDCache(hartId)(boom_params))
val dcache = LazyModule(new BoomNonBlockingDCache(staticIdForMetadataUseOnly)(boom_params))
val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcache.node
@@ -220,11 +222,11 @@ class BoomTraceGenTile private(
class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile)
extends BaseTileModuleImp(outer){
val status = IO(new GroundTestStatus)
val status = outer.statusNode.bundle
val halt_and_catch_fire = None
val tracegen = Module(new TraceGenerator(outer.params.traceParams))
tracegen.io.hartid := constants.hartid
tracegen.io.hartid := outer.hartIdSinkNode.bundle
val ptw = Module(new DummyPTW(1))
val lsu = Module(new LSU()(outer.boom_params, outer.dcache.module.edge))

2
tools/chisel3

Submodule tools/chisel3 updated: 21ea734d80...cc2971feb1

2
tools/firrtl

Submodule tools/firrtl updated: 7c6f58d986...c07da8a581