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3rd Revision

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This commit is contained in:
Zitao Fang
2020-07-12 01:08:13 -07:00
parent 9ad9d00a23
commit ced7ea634c
2 changed files with 25 additions and 20 deletions
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4
generators/chipyard/src/main/scala/example/TutorialTile.scala
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@@ -125,7 +125,7 @@ class MyTile(
Resource(cpuDevice, "reg").bind(ResourceAddress(hartId))
}
// (Connection to bus, interrupt, etc.)
// TODO: Create TileLink nodes and connections here.
// }
// DOC include end: Tile class
@@ -159,7 +159,7 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
// annotate the parameters
Annotated.params(this, outer.myParams)
// TODO: Create the top module of the core and connect it with the ports in "outer" }
// TODO: Create the top module of the core and connect it with the ports in "outer"
//}
// DOC include end: Implementation class