Merge branch 'dev' into diplomatic-clocks

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -25,7 +25,7 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.spi._
 
-import chipyard.{BuildTop, BuildSystem, ClockDrivers, ChipyardClockKey}
+import chipyard.{BuildTop, BuildSystem, ClockDrivers, ChipyardClockKey, TestSuitesKey, TestSuiteHelper}
 
 
 // -----------------------
@@ -44,9 +44,9 @@ class WithGPIO extends Config((site, here, up) => {
 })
 // DOC include end: gpio config fragment
 
-class WithUART extends Config((site, here, up) => {
+class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => {
   case PeripheryUARTKey => Seq(
-    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256))
+    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
 })
 
 class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => {
@@ -92,17 +92,19 @@ class WithMultiRoCC extends Config((site, here, up) => {
  *
  * @param harts harts to specify which will get a Hwacha
  */
-class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
-  case MultiRoCCKey => {
-    up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
-      (i -> Seq((p: Parameters) => {
-        val hwacha = LazyModule(new Hwacha()(p))
-        hwacha
-      }))
+class WithMultiRoCCHwacha(harts: Int*) extends Config(
+  new chipyard.config.WithHwachaTest ++
+  new Config((site, here, up) => {
+    case MultiRoCCKey => {
+      up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
+        (i -> Seq((p: Parameters) => {
+          val hwacha = LazyModule(new Hwacha()(p)).suggestName("hwacha")
+          hwacha
+        }))
+      }
     }
-  }
-})
-
+  })
+)
 
 class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
@@ -137,6 +139,18 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
   }
 })
 
+class WithHwachaTest extends Config((site, here, up) => {
+  case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => {
+    up(TestSuitesKey).apply(tileParams, suiteHelper, p)
+    import hwacha.HwachaTestSuites._
+    suiteHelper.addSuites(rv64uv.map(_("p")))
+    suiteHelper.addSuites(rv64uv.map(_("vp")))
+    suiteHelper.addSuite(rv64sv("p"))
+    suiteHelper.addSuite(hwachaBmarks)
+    "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha"
+  }
+})
+
 // The default RocketChip BaseSubsystem drives its diplomatic clock graph
 // with the implicit clocks of Subsystem. Don't do that, instead we extend
 // the diplomacy graph upwards into the ChipTop, where we connect it to

generators/chipyard/src/main/scala/TestSuites.scala

@@ -3,8 +3,8 @@ package chipyard
 import scala.collection.mutable.{LinkedHashSet}
 
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.tile.{XLen}
-import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.tile.{XLen, TileParams}
+import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
 import boom.common.{BoomTileAttachParams}
@@ -64,133 +64,51 @@ class TestSuiteHelper
   def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }
 
   /**
-  * Add BOOM tests (asm, bmark, regression)
+  * Add generic tests (asm, bmark, regression) for all cores.
   */
-  def addBoomTestSuites(implicit p: Parameters) = {
+  def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = {
     val xlen = p(XLen)
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
-      case tp: BoomTileAttachParams => {
-        val tileParams = tp.tileParams
-        val coreParams = tileParams.core
-        val vm = coreParams.useVM
-        val env = if (vm) List("p","v") else List("p")
-        coreParams.fpu foreach { case cfg =>
-          if (xlen == 32) {
-            addSuites(env.map(rv32uf))
-            if (cfg.fLen >= 64) {
-              addSuites(env.map(rv32ud))
-            }
-          } else if (cfg.fLen >= 64) {
+    tiles.find(_.hartId == 0).map { tileParams =>
+      val coreParams = tileParams.core
+      val vm = coreParams.useVM
+      val env = if (vm) List("p","v") else List("p")
+      coreParams.fpu foreach { case cfg =>
+        if (xlen == 32) {
+          addSuites(env.map(rv32uf))
+          if (cfg.fLen >= 64)
+            addSuites(env.map(rv32ud))
+        } else {
+          addSuite(rv32udBenchmarks)
+          addSuites(env.map(rv64uf))
+          if (cfg.fLen >= 64)
             addSuites(env.map(rv64ud))
-            addSuites(env.map(rv64uf))
-            addSuite(rv32udBenchmarks)
-          }
         }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          } else {
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-          }
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites(rvu.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
       }
-      case _ =>
-    }
-  }
-
-  /**
-  * Add Rocket tests (asm, bmark, regression)
-  */
-  def addRocketTestSuites(implicit p: Parameters) = {
-    val xlen = p(XLen)
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
-      case tp: RocketTileAttachParams => {
-        val tileParams = tp.tileParams
-        val coreParams = tileParams.core
-        val vm = coreParams.useVM
-        val env = if (vm) List("p","v") else List("p")
-        coreParams.fpu foreach { case cfg =>
-          if (xlen == 32) {
-            addSuites(env.map(rv32uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv32ud))
-          } else {
-            addSuite(rv32udBenchmarks)
-            addSuites(env.map(rv64uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv64ud))
-          }
-        }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          else
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+      if (coreParams.useAtomics) {
+        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
+          addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+        else
+          addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
       }
-      case _ =>
-    }
-  }
+      if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      val (rvi, rvu) =
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        else            ((if (vm) rv32i else rv32pi), rv32u)
 
-  /**
-  * Add Ariane tests (asm, bmark, regression)
-  */
-  def addArianeTestSuites(implicit p: Parameters) = {
-    val xlen = p(XLen)
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
-      case tp: ArianeTileAttachParams => {
-        val tileParams = tp.tileParams
-        val coreParams = tileParams.core
-        val vm = coreParams.useVM
-        val env = if (vm) List("p","v") else List("p")
-        coreParams.fpu foreach { case cfg =>
-          if (xlen == 32) {
-            addSuites(env.map(rv32uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv32ud))
-          } else {
-            addSuite(rv32udBenchmarks)
-            addSuites(env.map(rv64uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv64ud))
-          }
-        }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          else
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
-      }
-      case _ =>
+      addSuites(rvi.map(_("p")))
+      addSuites(rvu.map(_("p")))
+      addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      addSuite(benchmarks)
+      addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
     }
   }
 }
+
+/**
+ * Config key of custom test suite.
+ */
+case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => String]((tiles, helper, p) => {
+  helper.addGenericTestSuites(tiles)(p)
+  // Return an empty string as makefile additional snippets
+  ""
+})

generators/chipyard/src/main/scala/config/BoomConfigs.scala

@@ -19,7 +19,6 @@ class LargeBoomConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class MegaBoomConfig extends Config(
-  new boom.common.WithBoomBranchPrintf ++
   new boom.common.WithNMegaBooms(1) ++                           // mega boom config
   new chipyard.config.AbstractConfig)
 
@@ -28,6 +27,7 @@ class DualSmallBoomConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class HwachaLargeBoomConfig extends Config(
+  new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
   new boom.common.WithNLargeBooms(1) ++
   new chipyard.config.AbstractConfig)
@@ -43,4 +43,3 @@ class DromajoBoomConfig extends Config(
   new chipyard.config.WithTraceIO ++                             // enable the traceio
   new boom.common.WithNSmallBooms(1) ++
   new chipyard.config.AbstractConfig)
-

generators/chipyard/src/main/scala/config/HeteroConfigs.scala

@@ -13,6 +13,7 @@ class LargeBoomAndRocketConfig extends Config(
 
 // DOC include start: BoomAndRocketWithHwacha
 class HwachaLargeBoomAndHwachaRocketConfig extends Config(
+  new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                          // add hwacha to all harts
   new boom.common.WithNLargeBooms(1) ++                      // add 1 boom core
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++     // add 1 rocket core

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -11,6 +11,7 @@ class RocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class HwachaRocketConfig extends Config(
+  new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                        // use Hwacha vector accelerator
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/example/TutorialTile.scala

@@ -0,0 +1,236 @@
+package chipyard.example
+
+import chisel3._
+import chisel3.util._
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalTreeNode}
+import freechips.rocketchip.rocket._
+import freechips.rocketchip.subsystem.{RocketCrossingParams}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
+import freechips.rocketchip.util._
+import freechips.rocketchip.tile._
+import freechips.rocketchip.amba.axi4._
+
+// Example parameter class copied from Ariane, not included in documentation but for compile check only
+// If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure
+// out what parameters you need before you write the parameter class
+case class MyCoreParams(
+  bootFreqHz: BigInt = BigInt(1700000000),
+  rasEntries: Int = 4,
+  btbEntries: Int = 16,
+  bhtEntries: Int = 16,
+  enableToFromHostCaching: Boolean = false,
+) extends CoreParams {
+  val useVM: Boolean = true
+  val useUser: Boolean = true
+  val useSupervisor: Boolean = false
+  val useDebug: Boolean = true
+  val useAtomics: Boolean = true
+  val useAtomicsOnlyForIO: Boolean = false // copied from Rocket
+  val useCompressed: Boolean = true
+  override val useVector: Boolean = false
+  val useSCIE: Boolean = false
+  val useRVE: Boolean = false
+  val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket
+  val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket
+  val nLocalInterrupts: Int = 0
+  val nPMPs: Int = 0 // TODO: Check
+  val pmpGranularity: Int = 4 // copied from Rocket
+  val nBreakpoints: Int = 0 // TODO: Check
+  val useBPWatch: Boolean = false
+  val nPerfCounters: Int = 29
+  val haveBasicCounters: Boolean = true
+  val haveFSDirty: Boolean = false
+  val misaWritable: Boolean = false
+  val haveCFlush: Boolean = false
+  val nL2TLBEntries: Int = 512 // copied from Rocket
+  val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket
+  val mtvecWritable: Boolean = true // copied from Rocket
+  val instBits: Int = if (useCompressed) 16 else 32
+  val lrscCycles: Int = 80 // copied from Rocket
+  val decodeWidth: Int = 1 // TODO: Check
+  val fetchWidth: Int = 1 // TODO: Check
+  val retireWidth: Int = 2
+}
+
+// DOC include start: CanAttachTile
+case class MyTileAttachParams(
+  tileParams: MyTileParams,
+  crossingParams: RocketCrossingParams
+) extends CanAttachTile {
+  type TileType = MyTile
+  val lookup = PriorityMuxHartIdFromSeq(Seq(tileParams))
+}
+// DOC include end: CanAttachTile
+
+case class MyTileParams(
+  name: Option[String] = Some("my_tile"),
+  hartId: Int = 0,
+  trace: Boolean = false,
+  val core: MyCoreParams = MyCoreParams()
+) extends InstantiableTileParams[MyTile]
+{
+  val beuAddr: Option[BigInt] = None
+  val blockerCtrlAddr: Option[BigInt] = None
+  val btb: Option[BTBParams] = Some(BTBParams())
+  val boundaryBuffers: Boolean = false
+  val dcache: Option[DCacheParams] = Some(DCacheParams())
+  val icache: Option[ICacheParams] = Some(ICacheParams())
+  def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = {
+    new MyTile(this, crossing, lookup)
+  }
+}
+
+// DOC include start: Tile class
+class MyTile(
+  val myParams: MyTileParams,
+  crossing: ClockCrossingType,
+  lookup: LookupByHartIdImpl,
+  q: Parameters)
+  extends BaseTile(myParams, crossing, lookup, q)
+  with SinksExternalInterrupts
+  with SourcesExternalNotifications
+{
+
+  // Private constructor ensures altered LazyModule.p is used implicitly
+  def this(params: MyTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
+    this(params, crossing.crossingType, lookup, p)
+
+  // Require TileLink nodes
+  val intOutwardNode = IntIdentityNode()
+  val masterNode = visibilityNode
+  val slaveNode = TLIdentityNode()
+
+  // Implementation class (See below)
+  override lazy val module = new MyTileModuleImp(this)
+
+  // Required entry of CPU device in the device tree for interrupt purpose
+  val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("my-organization,my-cpu", "riscv")) {
+    override def parent = Some(ResourceAnchors.cpus)
+    override def describe(resources: ResourceBindings): Description = {
+      val Description(name, mapping) = super.describe(resources)
+      Description(name, mapping ++
+                        cpuProperties ++
+                        nextLevelCacheProperty ++
+                        tileProperties)
+    }
+  }
+
+  ResourceBinding {
+    Resource(cpuDevice, "reg").bind(ResourceAddress(hartId))
+  }
+
+  // TODO: Create TileLink nodes and connections here.
+  // DOC include end: Tile class
+  
+  // DOC include start: AXI4 node
+  // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more. 
+  val idBits = 4
+  val memAXI4Node = AXI4MasterNode(
+    Seq(AXI4MasterPortParameters(
+      masters = Seq(AXI4MasterParameters(
+        name = "myPortName",
+        id = IdRange(0, 1 << idBits))))))
+  val memoryTap = TLIdentityNode() // Every bus connection should have their own tap node
+  // DOC include end: AXI4 node
+
+  // DOC include start: AXI4 convert
+  (tlMasterXbar.node  // tlMasterXbar is the bus crossbar to be used when this core / tile is acting as a master; otherwise, use tlSlaveXBar
+    := memoryTap
+    := TLBuffer()
+    := TLFIFOFixer(TLFIFOFixer.all) // fix FIFO ordering
+    := TLWidthWidget(masterPortBeatBytes) // reduce size of TL
+    := AXI4ToTL() // convert to TL
+    := AXI4UserYanker(Some(2)) // remove user field on AXI interface. need but in reality user intf. not needed
+    := AXI4Fragmenter() // deal with multi-beat xacts
+    := memAXI4Node) // The custom node, see below
+  // DOC include end: AXI4 convert
+
+}
+
+// DOC include start: Implementation class
+class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
+  // annotate the parameters
+  Annotated.params(this, outer.myParams)
+
+  // TODO: Create the top module of the core and connect it with the ports in "outer"
+
+  // If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like 
+  //   val core = Module(new MyCoreBlackbox(params...)) 
+  // (as described in the blackbox tutorial) and connect appropriate signals. See the blackbox tutorial
+  // (link on the top of the page) for more info.
+  // You can look at https://github.com/ucb-bar/ariane-wrapper/blob/master/src/main/scala/ArianeTile.scala
+  // for a Verilog example.
+
+  // If your core is in Chisel, you can simply instantiate the top module here like other Chisel module
+  // and connect appropriate signal. You can even implement this class as your top module.
+  // See https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/common/tile.scala and
+  // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for 
+  // Chisel example.
+
+  // DOC include end: Implementation class
+
+  // DOC include start: connect interrupt
+  // For example, our core support debug interrupt and machine-level interrupt, and suppose the following two signals
+  // are the interrupt inputs to the core. (DO NOT COPY this code - if your core treat each type of interrupt differently,
+  // you need to connect them to different interrupt ports of your core)
+  val debug_i = Wire(Bool())
+  val mtip_i = Wire(Bool())
+  // We create a bundle here and decode the interrupt.
+  val int_bundle = new TileInterrupts()
+  outer.decodeCoreInterrupts(int_bundle)
+  debug_i := int_bundle.debug
+  mtip_i := int_bundle.meip & int_bundle.msip & int_bundle.mtip
+  // DOC include end: connect interrupt
+
+  // DOC include start: raise interrupt
+  // This is a demo. You should call these function according to your core
+  // Suppose that the following signal is from the decoder indicating a WFI instruction is received.
+  val wfi_o = Wire(Bool())
+  outer.reportWFI(Some(wfi_o))
+  // Suppose that the following signal indicate an unreconverable hardware error.
+  val halt_o = Wire(Bool())
+  outer.reportHalt(Some(halt_o))
+  // Suppose that our core never stall for a long time / stop retiring. Use None to indicate that this interrupt never fires.
+  outer.reportCease(None)
+  // DOC include end: raise interrupt
+
+  // DOC include start: AXI4 connect
+  outer.memAXI4Node.out foreach { case (out, edgeOut) =>
+    // Connect your module IO port to "out"
+    // The type of "out" here is AXI4Bundle, which is defined in generators/rocket-chip/src/main/scala/amba/axi4/Bundles.scala
+    // Please refer to this file for the definition of the ports.
+    // If you are using APB, check APBBundle in generators/rocket-chip/src/main/scala/amba/apb/Bundles.scala
+    // If you are using AHB, check AHBSlaveBundle or AHBMasterBundle in generators/rocket-chip/src/main/scala/amba/ahb/Bundles.scala
+    // (choose one depends on the type of AHB node you create)
+    // If you are using AXIS, check AXISBundle and AXISBundleBits in generators/rocket-chip/src/main/scala/amba/axis/Bundles.scala
+  }
+  // DOC include end: AXI4 connect
+
+}
+
+// DOC include start: Config fragment
+class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => {
+    // Calculate the next available hart ID (since hart ID cannot be duplicated)
+    val prev = up(TilesLocated(InSubsystem), site)
+    val idOffset = overrideIdOffset.getOrElse(prev.size)
+    // Create TileAttachParams for every core to be instantiated
+    (0 until n).map { i =>
+      MyTileAttachParams(
+        tileParams = MyTileParams(hartId = i + idOffset),
+        crossingParams = RocketCrossingParams()
+      )
+    } ++ prev
+  }
+  // Configurate # of bytes in one memory / IO transaction. For RV64, one load/store instruction can transfer 8 bytes at most.
+  case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
+  // The # of instruction bits. Use maximum # of bits if your core supports both 32 and 64 bits.
+  case XLen => 64
+})
+// DOC include end: Config fragment

generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala

@@ -15,14 +15,16 @@ import firrtl.options.Viewer.view
 import freechips.rocketchip.stage.RocketChipOptions
 import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
 import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
+import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem}
 import freechips.rocketchip.util.HasRocketChipStageUtils
 import freechips.rocketchip.tile.XLen
 
 import chipyard.TestSuiteHelper
+import chipyard.TestSuitesKey
 
 class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
   // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
-  // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). 
+  // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such).
   override val prerequisites = Seq(
     Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
     Dependency[freechips.rocketchip.stage.phases.AddDefaultTests])
@@ -33,25 +35,11 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS
     val suiteHelper = new TestSuiteHelper
     // Use Xlen as a proxy for detecting if we are a processor-like target
     // The underlying test suites expect this field to be defined
-    if (p.lift(XLen).nonEmpty) {
-      suiteHelper.addRocketTestSuites
-      suiteHelper.addBoomTestSuites
-      suiteHelper.addArianeTestSuites
-    }
+    val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams)
+    if (p.lift(XLen).nonEmpty)
+      // If a custom test suite is set up, use the custom test suite
+      annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))
 
-    // if hwacha parameter exists then generate its tests
-    // TODO: find a more elegant way to do this. either through
-    // trying to disambiguate BuildRoCC, having a AccelParamsKey,
-    // or having the Accelerator/Tile add its own tests
-    import hwacha.HwachaTestSuites._
-    if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
-      suiteHelper.addSuites(rv64uv.map(_("p")))
-      suiteHelper.addSuites(rv64uv.map(_("vp")))
-      suiteHelper.addSuite(rv64sv("p"))
-      suiteHelper.addSuite(hwachaBmarks)
-      annotations += CustomMakefragSnippet(
-        "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha")
-    }
     RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations
   }
 

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -70,7 +70,8 @@ class WithFireSimConfigTweaks extends Config(
   new WithFireSimSimpleClocks ++
   // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
   new WithBootROM ++
-  // Optional*: Removing this will require target-software changes to properly capture UART output
+  // Optional*: Removing this will require adjusting the UART baud rate and
+  // potential target-software changes to properly capture UART output
   new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
   // Required: Existing FAME-1 transform cannot handle black-box clock gates
   new WithoutClockGating ++
@@ -86,8 +87,8 @@ class WithFireSimConfigTweaks extends Config(
   new testchipip.WithTSI ++
   // Optional: Removing this will require using an initramfs under linux
   new testchipip.WithBlockDevice ++
-  // Required*:
-  new chipyard.config.WithUART
+  // Required*: Scale default baud rate with periphery bus frequency
+  new chipyard.config.WithUART(BigInt(3686400L))
 )
 
 /*******************************************************************************
@@ -118,6 +119,21 @@ class FireSimQuadRocketConfig extends Config(
   new WithFireSimConfigTweaks ++
   new chipyard.QuadRocketConfig)
 
+// A stripped down configuration that should fit on all supported hosts.
+// Flat to avoid having to reorganize the config class hierarchy to remove certain features 
+class FireSimSmallSystemConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithBootROM ++
+  new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
+  new WithoutClockGating ++
+  new WithoutTLMonitors ++
+  new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
+  new testchipip.WithTSI ++
+  new testchipip.WithBlockDevice ++
+  new chipyard.config.WithUART ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
+  new chipyard.RocketConfig)
 
 //*****************************************************************
 // Boom config, base off chipyard's LargeBoomConfig