Bump fesvr for better loadmem impl. Fix verilator loadmem support
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@@ -116,7 +116,6 @@ int main(int argc, char** argv)
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FILE * vcdfile = NULL;
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uint64_t start = 0;
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#endif
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char ** htif_argv = NULL;
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int verilog_plusargs_legal = 1;
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opterr = 1;
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@@ -252,10 +251,6 @@ done_processing:
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usage(argv[0]);
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return 1;
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}
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int htif_argc = 1 + argc - optind;
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htif_argv = (char **) malloc((htif_argc) * sizeof (char *));
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htif_argv[0] = argv[0];
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for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++];
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if (verbose)
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fprintf(stderr, "using random seed %u\n", random_seed);
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@@ -278,8 +273,8 @@ done_processing:
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#endif
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jtag = new remote_bitbang_t(rbb_port);
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dtm = new dtm_t(htif_argc, htif_argv);
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tsi = new tsi_t(htif_argc, htif_argv);
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dtm = new dtm_t(argc, argv);
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tsi = new tsi_t(argc, argv);
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signal(SIGTERM, handle_sigterm);
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@@ -364,6 +359,5 @@ done_processing:
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if (tsi) delete tsi;
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if (jtag) delete jtag;
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if (tile) delete tile;
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if (htif_argv) free(htif_argv);
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return ret;
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}
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Submodule toolchains/esp-tools/riscv-isa-sim updated: 13384cac1e...2bc65d1bf6
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