wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
1,958 Commits 2 Branches 0 Tags
d204ccd9fc1ec4fcc6de4f84c8db06e0500e55fa
Commit Graph

577 Commits

Author SHA1 Message Date
Abraham Gonzalez
ed6d10ac2b Merge remote-tracking branch 'origin/dev' into offchip-axi-setup 2021-03-08 21:20:26 -08:00
Abraham Gonzalez
ade8457870 First doc pass (no updated imgs) [ci skip] 2021-03-09 05:11:24 +00:00
Abraham Gonzalez
e4ccfe1bb9 Renaming updates | Have FireSim clocks request frequency by default 2021-03-08 23:43:00 +00:00
Abraham Gonzalez
6ab8f8f8fc Update FireSim to support harness clocks | Small config renaming 2021-03-08 22:03:07 +00:00
Jerry Zhao
d98d6d1875 Merge pull request #808 from ucb-bar/gemmini-bump 
Bump gemmini for config changes
 2021-03-07 18:59:03 -08:00
abejgonzalez
562d8e5116 Distinguish between implicit clock/reset and reference harnessClock/Reset | Don't use parameter system to pass referenceFreq 2021-03-05 16:31:18 -08:00
abejgonzalez
2b7e359326 Cleanup config + fragments | Remove reference clk div/rst catch in harness [ci skip] 2021-03-05 12:26:10 -08:00
abejgonzalez
60a616e320 1st pass at connecting to harness PLL | Put UART adapter on harnessClock/Reset 2021-03-05 00:08:02 -08:00
abejgonzalez
d2a6dd6822 Add support for harness pll 2021-03-04 23:31:57 -08:00
abejgonzalez
3d9cd61d16 Slightly cleaner implementation 2021-03-03 22:38:44 -08:00
Abraham Gonzalez
a165763350 Merge pull request #807 from ucb-bar/tile_clk_assignment_fix 
Use "tile" instead of "core" to assign freq's in WithTileFrequency config. fragment
 2021-03-03 13:30:33 -08:00
Abraham Gonzalez
3d962180be Cleanup | Fix BlockDevice clocking issues 2021-03-03 19:44:55 +00:00
Abraham Gonzalez
c52fce79ae Fix FireChip compilation | Remove extra DefaultSerialTL in bridges 2021-03-03 07:25:49 +00:00
abejgonzalez
f850df7a9f General renaming / cleanup 2021-03-02 22:58:05 -08:00
Abraham Gonzalez
1d287bede5 Enlarge serial width | Bugfix loadmem disable | Add TracerV 2021-03-03 02:43:38 +00:00
Jerry Zhao
ffcb3156c9 Add WithMultiRoCCFromBuildRoCC to make heterogeneous accelerator configs easier 2021-03-01 00:14:15 -08:00
Abraham Gonzalez
a3e22c78de First attempt at getting Offchip AXI port 2021-02-28 22:27:18 +00:00
Abraham Gonzalez
79eccceadd Small comments to Clocks.scala 2021-02-27 22:55:25 +00:00
Jerry Zhao
1e2f778a67 Bump gemmini for config changes 2021-02-25 23:00:39 -08:00
abejgonzalez
6145b1df40 Use "tile" instead of "core" to assign freq's 2021-02-25 21:25:03 -08:00
Jerry Zhao
2736e948ab Bump Gemmini for FP configs 2021-02-18 12:43:09 -08:00
Jerry Zhao
5966588d68 Merge pull request #790 from ucb-bar/simdram_timings 
Passing MBus clock frequency to SimDRAM
 2021-02-17 23:10:51 -08:00
Tynan McAuley
01948f6cb5 docs: Fix dual-BOOM-Rocket-Hwacha documentation 
The docs indicate that this should be a dual-BOOM and single-Rocket
config, with the Hwacha attached to the Rocket. However, the
'LargeBoomAndHwachaRocketConfig' config only has a single Rocket core.
Added the 'DualLargeBoomAndHwachaRocketConfig' config to accurately
reflect what's stated in the docs.

Additionally, this fixes hart numbering to place the Hwacha accelerator
on the Rocket core rather than on the BOOM core.
 2021-02-11 16:02:59 -08:00
Tynan McAuley
851df86aba docs: Fix dual-BOOM-single-Rocket documentation 
There were two problems here:
    1. The docs indicated that this should be a dual-BOOM and
       single-Rocket config, but the config actually had two Rocket
       cores.
    2. Since the doc include string was 'DualBoomAndRocket', it was
       accidentally matching against the 'DualBoomAndRocketOneHwacha'
       section, which comes first in the file.

So, I created a new 'DualLargeBoomAndSingleRocketConfig' config which
only has one Rocket core, and changed the doc include string to
'DualBoomAndSingleRocket'.
 2021-02-11 14:55:36 -08:00
Jerry Zhao
4c11e170b8 Use series of pipe Queues instead of ShiftQueue for adding AXI4 memory delay 2021-02-09 00:47:10 -08:00
Jerry Zhao
235b1e5dfd Give TraceGenConfigs an explicit mbus clock 2021-02-08 09:03:15 -08:00
Jerry Zhao
c85ffd2a59 Add support for manually adjusting DRAM latency with a ShiftQueue 2021-02-08 03:14:48 -08:00
Jerry Zhao
0593e92cb3 Passing MBus clock frequency to SimDRAM 2021-02-08 02:11:18 -08:00
alonamid
6dcd4f9afc WithFireSimFAME5 to allow non Rocket/BOOM build 2021-02-01 17:33:07 -08:00
Jerry Zhao
99a1c5d542 Update comment on GenerateReset 
ChipTop reset was standardized to be async for 1.4.0
 2021-01-30 19:47:27 -08:00
Albert Magyar
f7a98f23bc Merge pull request #756 from ucb-bar/16-largeboom 
Add 16-core LargeBOOM config to firechip
 2021-01-13 15:36:51 -08:00
Albert Magyar
c481dc2ee8 Add 16-core LargeBOOM config to firechip 
* Fix Jerry's comment on accidentally mixing multiple BOOM configs
 2021-01-12 23:12:10 -08:00
Jerry Zhao
f624609331 Merge remote-tracking branch 'origin/dev' into sodor-testchipip-bump 2021-01-10 23:46:30 -08:00
Jerry Zhao
4156bd8513 Bump testchipip and sodor | increase sodor SerialTL width for faster binary loading 2021-01-10 23:39:16 -08:00
Jerry Zhao
b1b230ba01 Fix ICache SPAD base addr to avoid conflicts with default SerialTL mem 2021-01-10 23:38:11 -08:00
abejgonzalez
5505aef30f Bump sifive-blocks 2021-01-08 10:56:30 -08:00
abejgonzalez
4d3ff26a73 Bump testchipip 2021-01-04 15:36:00 -08:00
abejgonzalez
a6ca3d21ad Bump testchipip 2020-12-28 16:07:57 -08:00
abejgonzalez
b1cedf2d61 Make TinyRocketConfig work with multi-clock work 2020-12-28 09:55:10 -08:00
abejgonzalez
ca723f1323 Merge branch 'dev' into local-fpga-support 2020-12-27 20:57:57 -08:00
Tim Snyder
0f47d80edb bump boom along same PR 2020-12-23 15:00:57 +00:00
Tim Snyder
e22350092b bump boom along same PR 2020-12-21 18:27:47 +00:00
Tim Snyder
29ab6301e0 bump sifive-cache for merged sifive/block-inclusivecache-sifive#15 
my previous bump duplicated an earlier PR
 2020-12-21 18:15:49 +00:00
Tim Snyder
72d084da8f update parameter classes for RC additions 2020-12-18 23:24:19 +00:00
Tim Snyder
a7e6de835a rm *XTypeKey. upstreamed to RC 2020-12-18 23:22:03 +00:00
Tim Snyder
cb558b5952 bump boom along same PR 2020-12-18 23:20:31 +00:00
Tim Snyder
a2ce14f8d3 Bump sodor for ucb-bar/riscv-sodor#60 2020-12-18 21:03:12 +00:00
Tim Snyder
2ce5f6a407 Bump cva6 for ucb-bar/cva6-wrapper#11 2020-12-18 20:54:31 +00:00
Tim Snyder
022dbf976f Bump boom along in the same PR 2020-12-18 20:52:30 +00:00
Tim Snyder
f7a372153a Bump hwacha for ucb-bar/hwacha#24 2020-12-18 20:52:00 +00:00