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First doc pass (no updated imgs) [ci skip]

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This commit is contained in:
Abraham Gonzalez
2021-03-09 05:11:24 +00:00
parent e4ccfe1bb9
commit ade8457870
5 changed files with 120 additions and 39 deletions
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2
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -157,11 +157,13 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
}
ports.map({ port =>
// DOC include start: HarnessClockInstantiatorEx
val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(
system.serdesser.get,
port,
p(HarnessClockInstantiatorKey).getClockBundle("mem_over_serial_tl_clock", memFreq),
th.harnessReset)
// DOC include end: HarnessClockInstantiatorEx
val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, port.clock, th.harnessReset.asBool)
when (success) { th.success := true.B }

2
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -213,6 +213,7 @@ class LBWIFRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include start: MulticlockAXIOverSerialConfig
class MulticlockAXIOverSerialConfig extends Config(
new chipyard.config.WithSystemBusFrequencyAsDefault ++
new chipyard.config.WithSystemBusFrequency(250) ++
@@ -233,3 +234,4 @@ class MulticlockAXIOverSerialConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(2) ++
new chipyard.config.AbstractConfig)
// DOC include end: MulticlockAXIOverSerialConfig