wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge pull request #807 from ucb-bar/tile_clk_assignment_fix

Browse Source 
Use "tile" instead of "core" to assign freq's in WithTileFrequency config. fragment
This commit is contained in:
Abraham Gonzalez
2021-03-03 13:30:33 -08:00
committed by GitHub
parent 43a408e043 6145b1df40
commit a165763350
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
generators/chipyard/src/main/scala/ConfigFragments.scala
View File

@@ -204,7 +204,7 @@ class WithTLBackingMemory extends Config((site, here, up) => {
case ExtTLMem => up(ExtMem, site) // enable TL backing memory
})
class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)
class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("tile", fMHz)
class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble