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Give TraceGenConfigs an explicit mbus clock

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This commit is contained in:
Jerry Zhao
2021-02-08 09:03:15 -08:00
parent c85ffd2a59
commit 235b1e5dfd
1 changed files with 2 additions and 0 deletions
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2
generators/chipyard/src/main/scala/config/TracegenConfigs.scala
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@@ -11,6 +11,8 @@ class AbstractTraceGenConfig extends Config(
new chipyard.config.WithTracegenSystem ++
new chipyard.config.WithNoSubsystemDrivenClocks ++
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++
new chipyard.config.WithMemoryBusFrequency(100.0) ++
new chipyard.config.WithPeripheryBusFrequency(100.0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.groundtest.GroundTestBaseConfig)