Merge remote-tracking branch 'origin/dev' into sodor-testchipip-bump

2021-01-10 23:46:30 -08:00
parent 4156bd8513 d1d7bb8f52
commit f624609331
69 changed files with 3309 additions and 46 deletions
--- a/generators/chipyard/src/main/scala/ChipTop.scala
+++ b/generators/chipyard/src/main/scala/ChipTop.scala
@@ -7,7 +7,7 @@ import scala.collection.mutable.{ArrayBuffer}
 import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
 import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
 import freechips.rocketchip.config.{Parameters, Field}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import chipyard.iobinders._

@@ -23,7 +23,7 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters)
 * drive clock and reset generation
 */

-class ChipTop(implicit p: Parameters) extends LazyModule
+class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
    with HasTestHarnessFunctions with HasIOBinders {
  // The system module specified by BuildSystem
  lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system")
--- a/generators/chipyard/src/main/scala/ConfigFragments.scala
+++ b/generators/chipyard/src/main/scala/ConfigFragments.scala
@@ -184,6 +184,15 @@ class WithNoDebug extends Config((site, here, up) => {
  case DebugModuleKey => None
 })

+class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => {
+  case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)
+})
+
+class WithTLBackingMemory extends Config((site, here, up) => {
+  case ExtMem => None // disable AXI backing memory
+  case ExtTLMem => up(ExtMem, site) // enable TL backing memory
+})
+
 class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)

 class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
--- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala
+++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala
@@ -70,3 +70,13 @@ class WithMulticlockCoherentBusTopology extends Config((site, here, up) => {
      l2 = site(BankedL2Key),
      sbusToMbusXType = site(SbusToMbusXTypeKey)))
 })
+
+class WithMulticlockIncoherentBusTopology extends Config((site, here, up) => {
+  case TLNetworkTopologyLocated(InSubsystem) => List(
+    JustOneBusTopologyParams(sbus = site(SystemBusKey)),
+    HierarchicalMulticlockBusTopologyParams(
+      pbus = site(PeripheryBusKey),
+      fbus = site(FrontBusKey),
+      cbus = site(ControlBusKey),
+      xTypes = SubsystemCrossingParams()))
+})
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -20,6 +20,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
  with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
  with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
  with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
+  with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
  with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
  with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
  with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
@@ -35,6 +36,7 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
  with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
  with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
  with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
+  with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
  with chipyard.example.CanHavePeripheryGCDModuleImp
  with freechips.rocketchip.util.DontTouch
 // DOC include end: DigitalTop
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -11,7 +11,7 @@ import chisel3.internal.sourceinfo.{SourceInfo}
 import freechips.rocketchip.prci._
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug}
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
 import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
@@ -31,7 +31,7 @@ trait CanHaveHTIF { this: BaseSubsystem =>
  // Advertise HTIF if system can communicate with fesvr
  if (this match {
    case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true
-    case _: HasPeripheryDebug if p(ExportDebug).dmi => true
+    case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true
    case _ => false
  }) {
    ResourceBinding {
--- a/generators/chipyard/src/main/scala/System.scala
+++ b/generators/chipyard/src/main/scala/System.scala
@@ -7,7 +7,7 @@ package chipyard

 import chisel3._

-import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.tilelink._
@@ -23,7 +23,8 @@ import freechips.rocketchip.util.{DontTouch}
 */
 class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
  with HasAsyncExtInterrupts
-  with CanHaveMasterAXI4MemPort
+  with CanHaveMasterTLMemPort // export TL port for outer memory
+  with CanHaveMasterAXI4MemPort // expose AXI port for outer mem
  with CanHaveMasterAXI4MMIOPort
  with CanHaveSlaveAXI4Port
 {
@@ -40,3 +41,50 @@ class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubs
  with HasRTCModuleImp
  with HasExtInterruptsModuleImp
  with DontTouch
+
+// ------------------------------------
+// TL Mem Port Mixin
+// ------------------------------------
+
+// Similar to ExtMem but instantiates a TL mem port
+case object ExtTLMem extends Field[Option[MemoryPortParams]](None)
+
+/** Adds a port to the system intended to master an TL DRAM controller. */
+trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
+
+  require(!(p(ExtTLMem).nonEmpty && p(ExtMem).nonEmpty),
+    "Can only have 1 backing memory port. Use ExtTLMem for a TL memory port or ExtMem for an AXI memory port.")
+
+  private val memPortParamsOpt = p(ExtTLMem)
+  private val portName = "tl_mem"
+  private val device = new MemoryDevice
+  private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
+
+  val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) =>
+    Seq.tabulate(nMemoryChannels) { channel =>
+      val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
+      val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))
+
+     TLSlavePortParameters.v1(
+       managers = Seq(TLSlaveParameters.v1(
+         address            = base.flatMap(_.intersect(filter)),
+         resources          = device.reg,
+         regionType         = RegionType.UNCACHED, // cacheable
+         executable         = true,
+         supportsGet        = TransferSizes(1, mbus.blockBytes),
+         supportsPutFull    = TransferSizes(1, mbus.blockBytes),
+         supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
+         beatBytes = memPortParams.beatBytes)
+   }
+ }).toList.flatten)
+
+ mbus.coupleTo(s"memory_controller_port_named_$portName") {
+   (memTLNode
+     :*= TLBuffer()
+     :*= TLSourceShrinker(1 << idBits)
+     :*= TLWidthWidget(mbus.beatBytes)
+     :*= _)
+  }
+
+  val mem_tl = InModuleBody { memTLNode.makeIOs() }
+}
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -50,6 +50,6 @@ class AbstractConfig extends Config(
  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
-  new chipyard.WithMulticlockCoherentBusTopology ++  // hierarchical buses including mbus+l2
+  new chipyard.WithMulticlockCoherentBusTopology ++              // hierarchical buses including mbus+l2
  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system

--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -11,6 +11,16 @@ class RocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
  new chipyard.config.AbstractConfig)

+class TinyRocketConfig extends Config(
+  new chipyard.config.WithTLSerialLocation(
+    freechips.rocketchip.subsystem.FBUS,
+    freechips.rocketchip.subsystem.PBUS) ++                       // attach TL serial adapter to f/p busses
+  new chipyard.WithMulticlockIncoherentBusTopology ++             // use incoherent bus topology
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++             // remove L2$
+  new freechips.rocketchip.subsystem.WithNoMemPort ++             // remove backing memory
+  new freechips.rocketchip.subsystem.With1TinyCore ++             // single tiny rocket-core
+  new chipyard.config.AbstractConfig)
+
 class HwachaRocketConfig extends Config(
  new chipyard.config.WithHwachaTest ++
  new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
@@ -179,7 +189,7 @@ class MMIORocketConfig extends Config(
 class MulticlockRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
  // Frequency specifications
-  new chipyard.config.WithTileFrequency(1600.0) ++       // Matches the maximum frequency of U540 
+  new chipyard.config.WithTileFrequency(1600.0) ++       // Matches the maximum frequency of U540
  new chipyard.config.WithSystemBusFrequency(800.0) ++   // Ditto
  new chipyard.config.WithMemoryBusFrequency(1000.0) ++  // 2x the U540 freq (appropriate for a 128b Mbus)
  new chipyard.config.WithPeripheryBusFrequency(100) ++  // Retains the default pbus frequency
--- a/generators/sifive-blocks
+++ b/generators/sifive-blocks
--- a/generators/testchipip
+++ b/generators/testchipip
--- a/generators/utilities/src/main/scala/Simulator.scala
+++ b/generators/utilities/src/main/scala/Simulator.scala
@@ -5,7 +5,7 @@ import java.io.File
 case class GenerateSimConfig(
  targetDir: String = ".",
  dotFName: String = "sim_files.f",
-  simulator: Simulator = VerilatorSimulator,
+  simulator: Option[Simulator] = Some(VerilatorSimulator)
 )

 sealed trait Simulator
@@ -20,17 +20,18 @@ trait HasGenerateSimConfig {
      .abbr("sim")
      .valueName("<simulator-name>")
      .action((x, c) => x match {
-        case "verilator" => c.copy(simulator = VerilatorSimulator)
-        case "vcs" => c.copy(simulator = VCSSimulator)
+        case "verilator" => c.copy(simulator = Some(VerilatorSimulator))
+        case "vcs" => c.copy(simulator = Some(VCSSimulator))
+        case "none" => c.copy(simulator = None)
        case _ => throw new Exception(s"Unrecognized simulator $x")
      })
-      .text("Name of simulator to generate files for (verilator, vcs)")
+      .text("Name of simulator to generate files for (verilator, vcs, none)")

    opt[String]("target-dir")
      .abbr("td")
      .valueName("<target-directory>")
      .action((x, c) => c.copy(targetDir = x))
-      .text("Target director to put files")
+      .text("Target directory to put files")

    opt[String]("dotFName")
      .abbr("df")
@@ -47,9 +48,10 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
    if (fname.takeRight(2) == ".h") {
      cfg.simulator match {
        // verilator needs to explicitly include verilator.h, so use the -FI option
-        case VerilatorSimulator => s"-FI ${fname}"
+        case Some(VerilatorSimulator) => s"-FI ${fname}"
        // vcs pulls headers in with +incdir, doesn't have anything like verilator.h
-        case VCSSimulator => ""
+        case Some(VCSSimulator) => ""
+        case None => ""
      }
    } else { // do nothing otherwise
      fname
@@ -81,7 +83,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
    out.write(text)
    out.close()
  }
-  def resources(sim: Simulator): Seq[String] = Seq(
+  def resources(sim: Option[Simulator]): Seq[String] = Seq(
    "/testchipip/csrc/SimSerial.cc",
    "/testchipip/csrc/testchip_tsi.cc",
    "/testchipip/csrc/testchip_tsi.h",
@@ -95,15 +97,30 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
    "/csrc/remote_bitbang.h",
    "/csrc/remote_bitbang.cc",
    "/vsrc/EICG_wrapper.v",
-  ) ++ (sim match { // simulator specific files to include
-    case VerilatorSimulator => Seq(
-      "/csrc/emulator.cc",
-      "/csrc/verilator.h",
-    )
-    case VCSSimulator => Seq(
-      "/vsrc/TestDriver.v",
-    )
-  })
+    ) ++ (sim match {
+      case None => Seq()
+      case _ => Seq(
+        "/testchipip/csrc/SimSerial.cc",
+        "/testchipip/csrc/SimDRAM.cc",
+        "/testchipip/csrc/mm.h",
+        "/testchipip/csrc/mm.cc",
+        "/testchipip/csrc/mm_dramsim2.h",
+        "/testchipip/csrc/mm_dramsim2.cc",
+        "/csrc/SimDTM.cc",
+        "/csrc/SimJTAG.cc",
+        "/csrc/remote_bitbang.h",
+        "/csrc/remote_bitbang.cc",
+      )
+    }) ++ (sim match { // simulator specific files to include
+      case Some(VerilatorSimulator) => Seq(
+        "/csrc/emulator.cc",
+        "/csrc/verilator.h",
+      )
+      case Some(VCSSimulator) => Seq(
+        "/vsrc/TestDriver.v",
+      )
+      case None => Seq()
+    })

  def writeBootrom(): Unit = {
    firrtl.FileUtils.makeDirectory("./bootrom/")