Slightly cleaner implementation

generators/chipyard/src/main/scala/HarnessBinders.scala

@@ -144,8 +144,19 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
 
     p(SerialTLKey).map({ sVal =>
-      require(sVal.axiDomainClockFreqMHz.isDefined)
-      val freqRequested = sVal.axiDomainClockFreqMHz.get
+      // currently only the harness AXI port supports a passthrough clock
+      require(sVal.axiMemOverSerialTLParams.isDefined)
+      val axiDomainParams = sVal.axiMemOverSerialTLParams.get
+
+      val memFreq = axiDomainParams.axiClockParams match {
+        case Some(clkParams) => {
+          BigInt(clkParams.clockFreqMHz.toInt)*1000000
+        }
+        case None => {
+          // get freq. from what the master bus specifies
+          system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(p(SerialTLAttachKey).masterWhere).dtsFrequency.get
+        }
+      }
 
       ports.map({ port =>
         val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(system.serdesser.get, port, th.harnessReset)
@@ -153,14 +164,13 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
         when (success) { th.success := true.B }
 
         // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
-        (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memAXI4Node.edges.in).map { case (axi_port, edge) =>
+        (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>
           val memSize = sVal.memParams.size
           val lineSize = p(CacheBlockBytes)
-          val mem = Module(new SimDRAM(memSize, lineSize, (freqRequested.toInt)*1000000, edge.bundle)).suggestName("simdram")
-          mem.io.axi <> axi_port
-          // use the clk from the ClockAndResetIO
-          mem.io.clock := port.passthrough_clock_reset.clock
-          mem.io.reset := port.passthrough_clock_reset.reset
+          val mem = Module(new SimDRAM(memSize, lineSize, memFreq, edge.bundle)).suggestName("simdram")
+          mem.io.axi <> axi_port.bits
+          mem.io.clock := axi_port.clock
+          mem.io.reset := axi_port.reset
         }
       })
     })

generators/chipyard/src/main/scala/IOBinders.scala

@@ -11,7 +11,7 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.{SimAXIMem}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
 import freechips.rocketchip.util._
-import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters, ClockParameters, ClockGroup}
+import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters, ClockParameters, ClockGroup, ClockBundle, ClockBundleParameters}
 import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
 
 import sifive.blocks.devices.gpio._
@@ -261,7 +261,7 @@ class WithSerialTLIOCells extends OverrideIOBinder({
 })
 
 class WithSerialTLAndPassthroughClockPunchthrough extends OverrideLazyIOBinder({
-  (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s =>
+  (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ serial_io =>
     implicit val p: Parameters = GetSystemParameters(system)
 
     val sys = system.asInstanceOf[BaseSubsystem]
@@ -269,20 +269,32 @@ class WithSerialTLAndPassthroughClockPunchthrough extends OverrideLazyIOBinder({
     require(p(SerialTLKey).isDefined)
     val sVal = p(SerialTLKey).get
 
-    require(sVal.axiDomainClockFreqMHz.isDefined)
-    val freqRequested = sVal.axiDomainClockFreqMHz.get
+    // currently only the harness AXI port supports a passthrough clock
+    require(sVal.axiMemOverSerialTLParams.isDefined)
+    val axiDomainParams = sVal.axiMemOverSerialTLParams.get
 
-    // request clock to pass along
-    val externalAXIDomainClkSinkNode = ClockSinkNode(Seq(ClockSinkParameters(take = Some(ClockParameters(freqMHz = freqRequested)))))
-    (externalAXIDomainClkSinkNode
-      := ClockGroup()(p, ValName("axi_mem_clock_domain"))
-      := sys.asyncClockGroupsNode)
-    def clockBundle = externalAXIDomainClkSinkNode.in.head._1
+    val clockSinkNode = axiDomainParams.axiClockParams.map({ clkParams =>
+      // request clock to pass along
+      val node = ClockSinkNode(Seq(ClockSinkParameters(take = Some(ClockParameters(freqMHz = clkParams.clockFreqMHz)))))
+      (node
+        := ClockGroup()(p, ValName("mem_over_serialtl_domain"))
+        := sys.asyncClockGroupsNode)
+      node
+    })
+
+    def clockBundle = clockSinkNode match {
+      case Some(node) => node.in.head._1
+      case None => {
+        val dontCareClockBundle = new ClockBundle(ClockBundleParameters())
+        dontCareClockBundle.clock := DontCare
+        dontCareClockBundle.reset := DontCare
+        dontCareClockBundle
+      }
+    }
 
     InModuleBody {
-      // 1st clock+reset is for offchip, 2nd clock (attached to serial io is the serial clock)
       val port = IO(new SerialAndPassthroughClockResetIO(sVal.width)).suggestName(s"serial_tl_passthrough_clk")
-      port.clocked_serial <> s
+      port.clocked_serial <> serial_io
       port.passthrough_clock_reset <> clockBundle
 
       // return the ports and no IO cells