Merge branch 'dev' into local-fpga-support

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -1,5 +1,6 @@
 package chipyard.config
 
+import scala.util.matching.Regex
 import chisel3._
 import chisel3.util.{log2Up}
 
@@ -11,6 +12,7 @@ import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, D
 import freechips.rocketchip.groundtest.{GroundTestSubsystem}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
+import freechips.rocketchip.tilelink.{HasTLBusParams}
 import freechips.rocketchip.util.{AsyncResetReg, Symmetric}
 import freechips.rocketchip.prci._
 
@@ -21,7 +23,7 @@ import hwacha.{Hwacha}
 import gemmini.{Gemmini, GemminiConfigs}
 
 import boom.common.{BoomTileAttachParams}
-import ariane.{ArianeTileAttachParams}
+import cva6.{CVA6TileAttachParams}
 
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
@@ -120,7 +122,7 @@ class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
-    case tp: ArianeTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
     case other => other
   }
@@ -149,6 +151,11 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
   }
 })
 
+// Replaces the L2 with a broadcast manager for maintaining coherence
+class WithBroadcastManager extends Config((site, here, up) => {
+  case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)
+})
+
 class WithHwachaTest extends Config((site, here, up) => {
   case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => {
     up(TestSuitesKey).apply(tileParams, suiteHelper, p)
@@ -192,6 +199,34 @@ class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {
   case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble
 })
 
+class WithSystemBusFrequencyAsDefault extends Config((site, here, up) => {
+  case DefaultClockFrequencyKey => (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toDouble
+})
+
+class BusFrequencyAssignment[T <: HasTLBusParams](re: Regex, key: Field[T]) extends Config((site, here, up) => {
+  case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++
+    Seq((cName: String) => site(key).dtsFrequency.flatMap { f =>
+      re.findFirstIn(cName).map {_ => (f / (1000 * 1000)).toDouble }
+    })
+})
+
+/**
+  * Provides a diplomatic frequency for all clock sinks with an unspecified
+  * frequency bound to each bus.
+  *
+  * For example, the L2 cache, when bound to the sbus, receives a separate
+  * clock that appears as "subsystem_sbus_<num>".  This fragment ensures that
+  * clock requests the same frequency as the sbus itself.
+  */
+
+class WithInheritBusFrequencyAssignments extends Config(
+  new BusFrequencyAssignment("subsystem_sbus_\\d+".r, SystemBusKey) ++
+  new BusFrequencyAssignment("subsystem_pbus_\\d+".r, PeripheryBusKey) ++
+  new BusFrequencyAssignment("subsystem_cbus_\\d+".r, ControlBusKey) ++
+  new BusFrequencyAssignment("subsystem_fbus_\\d+".r, FrontBusKey) ++
+  new BusFrequencyAssignment("subsystem_mbus_\\d+".r, MemoryBusKey)
+)
+
 /**
   * Mixins to specify crossing types between the 5 traditional TL buses
   *
@@ -221,16 +256,19 @@ class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site,
   * up the diplomatic graph to the clock sources.
   */
 class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+  case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })
 class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case MemoryBusKey => up(MemoryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+  case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })
 class WithSystemBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case SystemBusKey => up(SystemBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+  case SystemBusKey => up(SystemBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+})
+class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
+  case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })
 class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case ControlBusKey => up(ControlBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+  case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })
 
 class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))

generators/chipyard/src/main/scala/CustomBusTopologies.scala

@@ -13,14 +13,6 @@ import freechips.rocketchip.subsystem._
 
 // For subsystem/BusTopology.scala
 
-/**
-  * Keys that serve as a means to define crossing types from a Parameters instance
-  */
-case object SbusToMbusXTypeKey extends Field[ClockCrossingType](NoCrossing)
-case object SbusToCbusXTypeKey extends Field[ClockCrossingType](NoCrossing)
-case object CbusToPbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing())
-case object FbusToSbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing())
-
 // Biancolin: This, modified from Henry's email
 /** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */
 case class CoherentMulticlockBusTopologyParams(
@@ -36,17 +28,35 @@ case class CoherentMulticlockBusTopologyParams(
     (SBUS, L2,   TLBusWrapperConnection(xType = NoCrossing, driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()),
     (L2,  MBUS,  TLBusWrapperConnection.crossTo(
       xType = sbusToMbusXType,
-      driveClockFromMaster = Some(true),
+      driveClockFromMaster = None,
       nodeBinding = BIND_QUERY))
   )
 )
 
+// This differs from upstream only in that it does not use the legacy crossTo
+// and crossFrom functions, and it ensures driveClockFromMaster = None
+case class HierarchicalMulticlockBusTopologyParams(
+  pbus: PeripheryBusParams,
+  fbus: FrontBusParams,
+  cbus: PeripheryBusParams,
+  xTypes: SubsystemCrossingParams
+) extends TLBusWrapperTopology(
+  instantiations = List(
+    (PBUS, pbus),
+    (FBUS, fbus),
+    (CBUS, cbus)),
+  connections = List(
+    (SBUS, CBUS, TLBusWrapperConnection.  crossTo(xType = xTypes.sbusToCbusXType, driveClockFromMaster = None)),
+    (CBUS, PBUS, TLBusWrapperConnection.  crossTo(xType = xTypes.cbusToPbusXType, driveClockFromMaster = None)),
+    (FBUS, SBUS, TLBusWrapperConnection.crossFrom(xType = xTypes.fbusToSbusXType, driveClockFromMaster = None)))
+)
+
 // For subsystem/Configs.scala
 
 class WithMulticlockCoherentBusTopology extends Config((site, here, up) => {
   case TLNetworkTopologyLocated(InSubsystem) => List(
     JustOneBusTopologyParams(sbus = site(SystemBusKey)),
-    HierarchicalBusTopologyParams(
+    HierarchicalMulticlockBusTopologyParams(
       pbus = site(PeripheryBusKey),
       fbus = site(FrontBusKey),
       cbus = site(ControlBusKey),

generators/chipyard/src/main/scala/Subsystem.scala

@@ -56,6 +56,23 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
     case b: BoomTile => b.module.core.coreMonitorBundle
   }.toList
 
+
+  // Relying on [[TLBusWrapperConnection]].driveClockFromMaster for
+  // bus-couplings that are not asynchronous strips the bus name from the sink
+  // ClockGroup. This makes it impossible to determine which clocks are driven
+  // by which bus based on the member names, which is problematic when there is
+  // a rational crossing between two buses. Instead, provide all bus clocks
+  // directly from the asyncClockGroupsNode in the subsystem to ensure bus
+  // names are always preserved in the top-level clock names.
+  //
+  // For example, using a RationalCrossing between the Sbus and Cbus, and
+  // driveClockFromMaster = Some(true) results in all cbus-attached device and
+  // bus clocks to be given names of the form "subsystem_sbus_[0-9]*".
+  // Conversly, if an async crossing is used, they instead receive names of the
+  // form "subsystem_cbus_[0-9]*". The assignment below provides the latter names in all cases.
+  Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc =>
+    tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode }
+  }
   override lazy val module = new ChipyardSubsystemModuleImp(this)
 }
 

generators/chipyard/src/main/scala/TestSuites.scala

@@ -7,9 +7,6 @@ import freechips.rocketchip.tile.{XLen, TileParams}
 import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
-import boom.common.{BoomTileAttachParams}
-import ariane.{ArianeTileAttachParams}
-
 /**
  * A set of pre-chosen regression tests
  */

generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala

@@ -1,30 +0,0 @@
-
-package chipyard.clocking
-
-import chisel3._
-
-import freechips.rocketchip.config.{Parameters}
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.prci._
-import freechips.rocketchip.util.{ResetCatchAndSync}
-
-/**
-  * Instantiates a reset synchronizer on all clock-reset pairs in a clock group
-  */
-class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule {
-  val node = ClockGroupAdapterNode()
-  lazy val module = new LazyRawModuleImp(this) {
-    (node.out zip node.in).map { case ((oG, _), (iG, _)) =>
-      (oG.member.data zip iG.member.data).foreach { case (o, i) =>
-        o.clock := i.clock
-        o.reset := ResetCatchAndSync(i.clock, i.reset.asBool)
-      }
-    }
-  }
-}
-
-object ClockGroupResetSynchronizer {
-  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node
-}
-
-

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -43,7 +43,8 @@ class AbstractConfig extends Config(
   new chipyard.config.WithUART ++                                // add a UART
   new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
   new chipyard.config.WithNoSubsystemDrivenClocks ++             // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
-  new chipyard.config.WithPeripheryBusFrequencyAsDefault ++      // Unspecified clocks will match the frequency specified by the pbus dtsFrequency parameter
+  new chipyard.config.WithInheritBusFrequencyAssignments ++      // Unspecified clocks within a bus will receive the bus frequency if set
+  new chipyard.config.WithPeripheryBusFrequencyAsDefault ++      // Unspecified frequencies with match the pbus frequency (which is always set)
   new freechips.rocketchip.subsystem.WithJtagDTM ++              // set the debug module to expose a JTAG port
   new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
   new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)

generators/chipyard/src/main/scala/config/ArianeConfigs.scala

@@ -1,19 +0,0 @@
-package chipyard
-
-import chisel3._
-
-import freechips.rocketchip.config.{Config}
-
-// ---------------------
-// Ariane Configs
-// ---------------------
-
-class ArianeConfig extends Config(
-  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.config.AbstractConfig)
-
-class dmiArianeConfig extends Config(
-  new chipyard.harness.WithSerialAdapterTiedOff ++     // Tie off the serial port, override default instantiation of SimSerial
-  new chipyard.config.WithDMIDTM ++                    // have debug module expose a clocked DMI port
-  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/CVA6Configs.scala

@@ -0,0 +1,19 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+// ---------------------
+// CVA6 Configs
+// ---------------------
+
+class CVA6Config extends Config(
+  new cva6.WithNCVA6Cores(1) ++                    // single CVA6 core
+  new chipyard.config.AbstractConfig)
+
+class dmiCVA6Config extends Config(
+  new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial
+  new chipyard.config.WithDMIDTM ++                // have debug module expose a clocked DMI port
+  new cva6.WithNCVA6Cores(1) ++                    // single CVA6 core
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -1,6 +1,7 @@
 package chipyard
 
 import freechips.rocketchip.config.{Config}
+import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // --------------
 // Rocket Configs
@@ -185,13 +186,19 @@ class MMIORocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
-class DividedClockRocketConfig extends Config(
-  new chipyard.config.WithTileFrequency(200.0) ++
-  new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
+class MulticlockRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.WithMemoryBusFrequency(50.0) ++
-  new chipyard.config.WithAsynchrousMemoryBusCrossing ++
-  new testchipip.WithAsynchronousSerialSlaveCrossing ++
+  // Frequency specifications
+  new chipyard.config.WithTileFrequency(1600.0) ++       // Matches the maximum frequency of U540 
+  new chipyard.config.WithSystemBusFrequency(800.0) ++   // Ditto
+  new chipyard.config.WithMemoryBusFrequency(1000.0) ++  // 2x the U540 freq (appropriate for a 128b Mbus)
+  new chipyard.config.WithPeripheryBusFrequency(100) ++  // Retains the default pbus frequency
+  new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (800 MHz)
+  //  Crossing specifications
+  new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
+  new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
+  new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
+  new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
   new chipyard.config.AbstractConfig)
 
 class LBWIFRocketConfig extends Config(

generators/chipyard/src/main/scala/example/NodeTypes.scala

@@ -11,7 +11,7 @@ import testchipip.TLHelper
 
 // DOC include start: MyClient
 class MyClient(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeClientNode(TLClientParameters(
+  val node = TLHelper.makeClientNode(TLMasterParameters.v1(
     name = "my-client",
     sourceId = IdRange(0, 4),
     requestFifo = true,
@@ -29,7 +29,7 @@ class MyClient(implicit p: Parameters) extends LazyModule {
 class MyManager(implicit p: Parameters) extends LazyModule {
   val device = new SimpleDevice("my-device", Seq("tutorial,my-device0"))
   val beatBytes = 8
-  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
     address = Seq(AddressSet(0x20000, 0xfff)),
     resources = device.reg,
     regionType = RegionType.UNCACHED,
@@ -83,7 +83,7 @@ class MyClientGroup(implicit p: Parameters) extends LazyModule {
 
 // DOC include start: MyManagerGroup
 class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
     address = Seq(AddressSet(0x0, 0xfff))))
 
   lazy val module = new LazyModuleImp(this) {
@@ -92,7 +92,7 @@ class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
     address = Seq(AddressSet(0x1000, 0xfff))))
 
   lazy val module = new LazyModuleImp(this) {

generators/chipyard/src/main/scala/example/TutorialTile.scala

@@ -15,8 +15,9 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.prci.ClockSinkParameters
 
-// Example parameter class copied from Ariane, not included in documentation but for compile check only
+// Example parameter class copied from CVA6, not included in documentation but for compile check only
 // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure
 // out what parameters you need before you write the parameter class
 case class MyCoreParams(
@@ -39,16 +40,20 @@ case class MyCoreParams(
   val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket
   val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket
   val nLocalInterrupts: Int = 0
+  val useNMI: Boolean = false
   val nPMPs: Int = 0 // TODO: Check
   val pmpGranularity: Int = 4 // copied from Rocket
   val nBreakpoints: Int = 0 // TODO: Check
   val useBPWatch: Boolean = false
+  val mcontextWidth: Int = 0
+  val scontextWidth: Int = 0
   val nPerfCounters: Int = 29
   val haveBasicCounters: Boolean = true
   val haveFSDirty: Boolean = false
   val misaWritable: Boolean = false
   val haveCFlush: Boolean = false
   val nL2TLBEntries: Int = 512 // copied from Rocket
+  val nL2TLBWays: Int = 1
   val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket
   val mtvecWritable: Boolean = true // copied from Rocket
   val instBits: Int = if (useCompressed) 16 else 32
@@ -81,6 +86,7 @@ case class MyTileParams(
   val boundaryBuffers: Boolean = false
   val dcache: Option[DCacheParams] = Some(DCacheParams())
   val icache: Option[ICacheParams] = Some(ICacheParams())
+  val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
   def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = {
     new MyTile(this, crossing, lookup)
   }
@@ -127,9 +133,9 @@ class MyTile(
 
   // TODO: Create TileLink nodes and connections here.
   // DOC include end: Tile class
-  
+
   // DOC include start: AXI4 node
-  // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more. 
+  // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more.
   val idBits = 4
   val memAXI4Node = AXI4MasterNode(
     Seq(AXI4MasterPortParameters(
@@ -160,17 +166,17 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
 
   // TODO: Create the top module of the core and connect it with the ports in "outer"
 
-  // If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like 
-  //   val core = Module(new MyCoreBlackbox(params...)) 
+  // If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like
+  //   val core = Module(new MyCoreBlackbox(params...))
   // (as described in the blackbox tutorial) and connect appropriate signals. See the blackbox tutorial
   // (link on the top of the page) for more info.
-  // You can look at https://github.com/ucb-bar/ariane-wrapper/blob/master/src/main/scala/ArianeTile.scala
+  // You can look at https://github.com/ucb-bar/cva6-wrapper/blob/master/src/main/scala/CVA6Tile.scala
   // for a Verilog example.
 
   // If your core is in Chisel, you can simply instantiate the top module here like other Chisel module
   // and connect appropriate signal. You can even implement this class as your top module.
   // See https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/common/tile.scala and
-  // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for 
+  // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for
   // Chisel example.
 
   // DOC include end: Implementation class

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -4,12 +4,13 @@ package firesim.firesim
 
 import chisel3._
 import chisel3.experimental.annotate
+import chisel3.util.experimental.BoringUtils
 
 import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle}
-import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem}
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.{RocketTile}
 import sifive.blocks.devices.uart._
 
@@ -22,7 +23,7 @@ import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotatio
 import firesim.bridges._
 import firesim.configs.MemModelKey
 import tracegen.{TraceGenSystemModuleImp}
-import ariane.ArianeTile
+import cva6.CVA6Tile
 
 import boom.common.{BoomTile}
 import barstools.iocell.chisel._
@@ -86,7 +87,12 @@ class WithNICBridge extends OverrideHarnessBinder({
 
 class WithUARTBridge extends OverrideHarnessBinder({
   (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) =>
-    ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil
+    val uartSyncClock = Wire(Clock())
+    uartSyncClock := false.B.asClock
+    val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode
+    val pbusClock = pbusClockNode.in.head._1.clock
+    BoringUtils.bore(pbusClock, Seq(uartSyncClock))
+    ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil
 })
 
 class WithBlockDeviceBridge extends OverrideHarnessBinder({

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -128,7 +128,7 @@ class FireSimQuadRocketConfig extends Config(
   new chipyard.QuadRocketConfig)
 
 // A stripped down configuration that should fit on all supported hosts.
-// Flat to avoid having to reorganize the config class hierarchy to remove certain features 
+// Flat to avoid having to reorganize the config class hierarchy to remove certain features
 class FireSimSmallSystemConfig extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
@@ -188,21 +188,19 @@ class SupernodeFireSimRocketConfig extends Config(
   new FireSimRocketConfig)
 
 //**********************************************************************************
-//* Ariane Configurations
+//* CVA6 Configurations
 //*********************************************************************************/
-class FireSimArianeConfig extends Config(
+class FireSimCVA6Config extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks ++
-  new chipyard.ArianeConfig)
+  new chipyard.CVA6Config)
 
 //**********************************************************************************
 //* Multiclock Configurations
 //*********************************************************************************/
 class FireSimMulticlockRocketConfig extends Config(
   new chipyard.config.WithTileFrequency(6400.0) ++ //lol
-  new WithDefaultFireSimBridges ++
-  new WithDefaultMemModel ++
-  new WithFireSimConfigTweaks ++
-  new chipyard.DividedClockRocketConfig)
+  new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
+  new FireSimRocketConfig)
 

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -42,10 +42,9 @@ abstract class FireSimTestSuite(
   }
 
   def runTest(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
-    behavior of s"${name} running on ${backend} in MIDAS-level simulation"
     compileMlSimulator(backend, debug)
     if (isCmdAvailable(backend)) {
-      it should s"pass" in {
+      it should s"pass in ML simulation on ${backend}" in {
         assert(invokeMlSimulator(backend, name, debug, additionalArgs) == 0)
       }
     }
@@ -59,13 +58,15 @@ abstract class FireSimTestSuite(
         case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv"
         case _ => ""
       }
-      val results = suite.names.toSeq sliding (N, N) map { t =>
-        val subresults = t map (name =>
-          Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug)))
-        Await result (Future sequence subresults, Duration.Inf)
-      }
-      results.flatten foreach { case (name, exitcode) =>
-        it should s"pass $name" in { assert(exitcode == 0) }
+      it should s"pass all tests in ${suite.makeTargetName}" in {
+        val results = suite.names.toSeq sliding (N, N) map { t =>
+          val subresults = t map (name =>
+            Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug)))
+          Await result (Future sequence subresults, Duration.Inf)
+        }
+        results.flatten foreach { case (name, exitcode) =>
+          assert(exitcode == 0, "Failed $name")
+        }
       }
     } else {
       ignore should s"pass $backend"
@@ -96,7 +97,9 @@ abstract class FireSimTestSuite(
     }
   }
 
-  clean
+  mkdirs
+  behavior of s"Tuple: ${targetTuple}"
+  elaborateAndCompile()
   runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0"""))
   runSuite("verilator")(benchmarks)
 }
@@ -110,7 +113,7 @@ class RocketMulticlockF1Tests extends FireSimTestSuite(
   "FireSimMulticlockRocketConfig",
   "WithSynthAsserts_BaseF1Config")
 
-class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config")
+class CVA6F1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimCVA6Config", "BaseF1Config")
 
 // This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call.
 class CITests extends Suites(

generators/tracegen/src/main/scala/Tile.scala

@@ -13,6 +13,7 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.subsystem._
 import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO}
 import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule}
+import freechips.rocketchip.prci.ClockSinkParameters
 
 
 class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
@@ -190,6 +191,7 @@ case class BoomTraceGenParams(
   val blockerCtrlAddr = None
   val name = None
   val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId)
+  val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
 }
 
 class BoomTraceGenTile private(