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Fix FireChip compilation | Remove extra DefaultSerialTL in bridges

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This commit is contained in:
Abraham Gonzalez
2021-03-03 07:25:49 +00:00
parent f850df7a9f
commit c52fce79ae
2 changed files with 15 additions and 13 deletions
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6
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -98,13 +98,13 @@ class WithUARTBridge extends OverrideHarnessBinder({
class WithBlockDeviceBridge extends OverrideHarnessBinder({
(system: CanHavePeripheryBlockDevice, th: FireSim, ports: Seq[ClockedIO[BlockDeviceIO]]) => {
implicit val p: Parameters = GetSystemParameters(system)
ports.map { b => BlockDevBridge(b.clock, b.bits, th.harnessReset.toBool) }
ports.map { b => BlockDevBridge(b.clock, b.bits, th.harnessReset.asBool) }
Nil
}
})
class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[SerialAndPassthroughClockResetIO]]]) => {
(system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[SerialAndPassthroughClockResetIO]) => {
implicit val p = GetSystemParameters(system)
p(SerialTLKey).map({ sVal =>
@@ -113,7 +113,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
ports.map({ port =>
val offchipNetwork = SerialAdapter.connectHarnessMultiClockAXIRAM(system.serdesser.get, port, th.harnessReset)
SerialBridge(port.clocked_serial.clock, offchipNetwork.module.io.tsi_ser, MainMemoryConsts.globalName)
SerialBridge(port.clocked_serial.clock, offchipNetwork.module.io.tsi_ser, Some(MainMemoryConsts.globalName))
// connect SimAxiMem
(offchipNetwork.mem_axi4 zip offchipNetwork.memAXI4Node.edges.in).map { case (axi4, edge) =>

22
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -74,10 +74,6 @@ class WithFireSimConfigTweaksWithoutClocking extends Config(
new chipyard.config.WithTraceIO ++
// Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
// Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
// for signalling simulation termination under simulation success. This fragment can
// be removed if you supply an auxiliary bridge that signals simulation termination
new testchipip.WithDefaultSerialTL ++
// Optional: Removing this will require using an initramfs under linux
new testchipip.WithBlockDevice ++
// Required*: Scale default baud rate with periphery bus frequency
@@ -220,24 +216,30 @@ class FireSim16LargeBoomConfig extends Config(
new boom.common.WithNLargeBooms(16) ++
new chipyard.config.AbstractConfig)
class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
class WithOffchipAXINoClksSetup(pbusFreqMHz: BigInt = 3200) extends Config(
//new chipyard.config.WithUART((pbusFreqMHz / 100) * BigInt(115200L)) ++
new chipyard.config.WithUART(BigInt(3686400L)) ++
)
// unsure if this needs to scale
//new chipyard.config.WithUART((pbusFreqMHz / 100) * BigInt(115200L)) ++
//class FireSimDebugOffchipConfig extends Config(
// new WithTracerV ++
// new WithOffchipAXINoClksSetup(3200) ++
// new chipyard.DebugOffchipConfig
//)
//
//class FireSimDebugOffchip2Config extends Config(
// new WithTracerV ++
// new WithOffchipAXINoClksSetup(3200) ++
// new chipyard.DebugOffchip2Config
//)
class FireSimDebugOffchip2Config extends Config(
new chipyard.config.WithUART((4000 / 100) * BigInt(115200L)) ++
new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaksWithoutClocking ++ // don't inherit firesim clocking
new chipyard.DebugOffchip3Config
)
class FireSimDebugOffchip3Config extends Config(
new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial
new WithDefaultFireSimBridges ++