Jerry Zhao
|
b8e95e0305
|
Rename implicit clock/reset to referenceclock/reset
|
2023-05-12 15:11:44 -07:00 |
|
Jerry Zhao
|
94d471bd9a
|
Set firesim harnessbinder freq to 1000 MHz by default
|
2023-05-12 14:44:07 -07:00 |
|
Jerry Zhao
|
85bb945555
|
Fix bug in cospike
|
2023-05-12 11:34:31 -07:00 |
|
Jerry Zhao
|
7ae43a1829
|
Fix tracegenconfig
|
2023-05-12 10:51:34 -07:00 |
|
Jerry Zhao
|
b42a3d4896
|
Make Passthrough clock assert more verbose
|
2023-05-12 10:51:27 -07:00 |
|
Jerry Zhao
|
607c2b5a73
|
Unify multi-node btw chipyard/firechip | unify harness clocking
|
2023-05-12 08:41:34 -07:00 |
|
Jerry Zhao
|
0cbca54e19
|
Remove TestChipBusFreqs (this is ChipLikeRocketConfig)
|
2023-05-12 00:03:36 -07:00 |
|
Jerry Zhao
|
64ad77bbcf
|
Make FPGA flows use the harnessClockInstantiator
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
|
a9bc11accb
|
Update comments on harnessbinders in AbstractConfig
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
|
1a6b34696e
|
Set a more realistic 500 MHz uncore clock:
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
|
4dd017d181
|
Fix WithClockAndResetFromHarness to actually request harness clocks
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
|
f4bf1b0a28
|
Fix multiclockrocketconfig
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
|
624785376a
|
Fix PassThroughClockGenerator to handle multiclock properly
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
|
ffc4d1f662
|
Use getClass.getSimpleName for ClockSourceAtFreqMHz blackbox inline
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
|
1916d3e4fc
|
Add timeunit to ClockSourceAtFreqMHz
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
|
bcd273986f
|
Fix ClockSourceAtFreqMHz period calc
|
2023-05-11 15:04:03 -07:00 |
|
Jerry Zhao
|
5c8ea080ee
|
Switch to our own ClockSourceAtFreq that is verilator-compatible
|
2023-05-11 15:04:03 -07:00 |
|
Jerry Zhao
|
71fe1ad858
|
Switch RTL sims to absolute clock-generators
|
2023-05-11 15:04:03 -07:00 |
|
Jerry Zhao
|
c148f1daf1
|
Make BootAddrReg optional
|
2023-05-10 11:44:03 -07:00 |
|
Jerry Zhao
|
fbfb518b72
|
Merge remote-tracking branch 'origin/main' into renameserial
|
2023-05-10 11:39:11 -07:00 |
|
Sagar Karandikar
|
1c10f75622
|
Merge pull request #1471 from ucb-bar/lowmem-configs
Add 1GB / 4GB DRAM firechip configs for FireSim VCU118
|
2023-05-10 11:32:01 -07:00 |
|
Sagar Karandikar
|
abe8a7fb8b
|
remove extra newlines
|
2023-05-10 11:31:05 -07:00 |
|
abejgonzalez
|
2997cddc0e
|
Merge remote-tracking branch 'origin/main' into bump-verilator
|
2023-05-09 13:27:13 -07:00 |
|
Jerry Zhao
|
eced8e63d9
|
Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness
|
2023-05-08 18:19:18 -07:00 |
|
Sagar Karandikar
|
95da9cefb5
|
4GB DRAM configs
|
2023-05-08 13:41:51 -07:00 |
|
Jerry Zhao
|
ac281daa78
|
Move TestHarness to chipyard.harness, make chipyard/harness directory
|
2023-05-08 08:00:56 -07:00 |
|
Jerry Zhao
|
4f5bbdca97
|
Flip serial_tl.clock for firechip BridgeBinders
|
2023-05-07 22:22:37 -07:00 |
|
Jerry Zhao
|
9566667767
|
Remove bus-to-bus crossings
|
2023-05-07 22:22:37 -07:00 |
|
Jerry Zhao
|
5f076b184d
|
Flip serial_tl_clock to be generated off-chip
|
2023-05-07 22:22:36 -07:00 |
|
Jerry Zhao
|
4eb0f81c16
|
Bump testchipip
|
2023-05-07 16:02:23 -07:00 |
|
Jerry Zhao
|
954dab1638
|
Merge remote-tracking branch 'origin/main' into tcdtm
|
2023-05-07 15:56:55 -07:00 |
|
Sagar Karandikar
|
40d0a1f3bd
|
low mem configs
|
2023-05-07 11:47:14 -07:00 |
|
Jerry Zhao
|
2271194131
|
Merge remote-tracking branch 'origin/main' into bump-fs
|
2023-05-06 19:26:20 -07:00 |
|
Jerry Zhao
|
257e7d7507
|
Check that HarnessClockInstantiator doesn't receive requests for similarly-named-clocks with different frequencies (#1460)
|
2023-05-05 17:09:07 -07:00 |
|
Jerry Zhao
|
b8ccb7d4f6
|
Support not instantiating the TileClockGater/ResetSetter PRCI controllers (#1459)
|
2023-05-04 17:15:38 -07:00 |
|
Jerry Zhao
|
b05f36df79
|
Fix support for no-bootROM systems (#1458)
|
2023-05-03 18:23:36 -07:00 |
|
Jerry Zhao
|
1cc5ea5192
|
Fix no-uart configs (#1457)
|
2023-05-03 18:23:16 -07:00 |
|
Jerry Zhao
|
a299dae1a5
|
Initialize cospike memory from SimDRAM memory
|
2023-05-01 09:28:55 -07:00 |
|
Tianrui Wei
|
64e8f334ac
|
fix: address comments
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
|
2023-04-20 16:19:16 -07:00 |
|
Tianrui Wei
|
c5002ab9d3
|
fix: address comments
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
|
2023-04-20 16:10:40 -07:00 |
|
Tianrui Wei
|
91ccc7b25d
|
feat: cospike changes
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
|
2023-04-20 15:42:08 -07:00 |
|
abejgonzalez
|
2bf8f258ad
|
Bump Gemmini
|
2023-04-20 13:22:19 -07:00 |
|
Jerry Zhao
|
6701b85f27
|
Bump testchipip
|
2023-04-19 23:48:14 -07:00 |
|
Jerry Zhao
|
104a5299a9
|
Fix typos
|
2023-04-19 19:52:46 -07:00 |
|
Jerry Zhao
|
383a0fee96
|
Bump testchipip to standardize tlserdes bundle params
|
2023-04-19 11:44:20 -07:00 |
|
Jerry Zhao
|
2b3c5fc48e
|
Merge remote-tracking branch 'origin/main' into tcdtm
|
2023-04-17 18:14:43 -07:00 |
|
Jerry Zhao
|
4038217ae9
|
Serial-TL backing memory configs should use 1 memory channel
|
2023-04-17 17:56:44 -07:00 |
|
Jerry Zhao
|
c6bf50bc9d
|
Update verilator's emulator.cc SIM_FILE_REQS
|
2023-04-17 16:20:52 -07:00 |
|
Jerry Zhao
|
ad9ea333d1
|
Bump TestChipIp to improve default serial_tl behavior
|
2023-04-17 14:14:24 -07:00 |
|
Jerry Zhao
|
8c47f50a73
|
Restore vector state as well for cosim loadarch
|
2023-04-17 14:07:37 -07:00 |
|