Rename implicit clock/reset to referenceclock/reset

generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala

@@ -53,8 +53,8 @@ trait HasHarnessInstantiators {
   val harnessBinderReset = Wire(Reset())
 
   // classes which inherit this trait should provide the below definitions
-  def implicitClock: Clock
-  def implicitReset: Reset
+  def referenceClock: Clock
+  def referenceReset: Reset
   def success: Bool
 
   // This can be accessed to get new clocks from the harness
@@ -86,9 +86,9 @@ trait HasHarnessInstantiators {
     val harnessBinderClk = harnessClockInstantiator.requestClockMHz("harnessbinder_clock", getHarnessBinderClockFreqMHz)
     println(s"Harness binder clock is $harnessBinderClockFreq")
     harnessBinderClock := harnessBinderClk
-    harnessBinderReset := implicitReset
+    harnessBinderReset := ResetCatchAndSync(harnessBinderClk, referenceReset.asBool)
 
-    harnessClockInstantiator.instantiateHarnessClocks(implicitClock)
+    harnessClockInstantiator.instantiateHarnessClocks(referenceClock)
 
     lazyDuts
   }

generators/chipyard/src/main/scala/harness/TestHarness.scala

@@ -24,8 +24,8 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessInst
   val success = WireInit(false.B)
   io.success := success
 
-  def implicitClock = clock
-  def implicitReset = reset
+  def referenceClock = clock
+  def referenceReset = reset
 
   instantiateChipTops()
 }

generators/firechip/src/main/scala/FireSim.scala

@@ -72,8 +72,8 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
   // In effect, the bridge counts the length of the reset in terms of this clock.
   resetBridge.io.clock := harnessBinderClock
 
-  def implicitClock = false.B.asClock // unused
-  def implicitReset = resetBridge.io.reset
+  def referenceClock = false.B.asClock // unused
+  def referenceReset = resetBridge.io.reset
   def success = { require(false, "success should not be used in Firesim"); false.B }
 
   instantiateChipTops()