Jerry Zhao
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a89b86c785
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Update HarnessClocking docs
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2023-05-12 15:21:27 -07:00 |
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Jerry Zhao
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b8e95e0305
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Rename implicit clock/reset to referenceclock/reset
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2023-05-12 15:11:44 -07:00 |
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Jerry Zhao
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94d471bd9a
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Set firesim harnessbinder freq to 1000 MHz by default
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2023-05-12 14:44:07 -07:00 |
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Jerry Zhao
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85bb945555
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Fix bug in cospike
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2023-05-12 11:34:31 -07:00 |
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Jerry Zhao
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7ae43a1829
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Fix tracegenconfig
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2023-05-12 10:51:34 -07:00 |
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Jerry Zhao
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b42a3d4896
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Make Passthrough clock assert more verbose
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2023-05-12 10:51:27 -07:00 |
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Jerry Zhao
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607c2b5a73
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Unify multi-node btw chipyard/firechip | unify harness clocking
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2023-05-12 08:41:34 -07:00 |
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Jerry Zhao
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0cbca54e19
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Remove TestChipBusFreqs (this is ChipLikeRocketConfig)
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2023-05-12 00:03:36 -07:00 |
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Jerry Zhao
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27f78da07b
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Merge pull request #1472 from ucb-bar/simpleclocks
Switch RTL sims to absolute clock-generators
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2023-05-11 21:36:53 -07:00 |
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Jerry Zhao
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d673c61b8b
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Switch SpikeTile CI to SpikeConfig
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2023-05-11 17:19:17 -07:00 |
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Jerry Zhao
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64ad77bbcf
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Make FPGA flows use the harnessClockInstantiator
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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a9bc11accb
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Update comments on harnessbinders in AbstractConfig
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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1a6b34696e
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Set a more realistic 500 MHz uncore clock:
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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4dd017d181
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Fix WithClockAndResetFromHarness to actually request harness clocks
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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f4bf1b0a28
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Fix multiclockrocketconfig
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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624785376a
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Fix PassThroughClockGenerator to handle multiclock properly
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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ffc4d1f662
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Use getClass.getSimpleName for ClockSourceAtFreqMHz blackbox inline
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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1916d3e4fc
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Add timeunit to ClockSourceAtFreqMHz
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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bcd273986f
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Fix ClockSourceAtFreqMHz period calc
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2023-05-11 15:04:03 -07:00 |
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Jerry Zhao
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5c8ea080ee
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Switch to our own ClockSourceAtFreq that is verilator-compatible
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2023-05-11 15:04:03 -07:00 |
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Jerry Zhao
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71fe1ad858
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Switch RTL sims to absolute clock-generators
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2023-05-11 15:04:03 -07:00 |
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Jerry Zhao
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335a50d074
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Merge pull request #1473 from ucb-bar/jerryz123-patch-1
Fix vcd/fst/fsdb waveform generation
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2023-05-10 16:04:58 -07:00 |
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Jerry Zhao
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a0569208a5
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Fix VCS waveforms
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2023-05-10 15:49:59 -07:00 |
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Jerry Zhao
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ab6479641e
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Fix verilator vcd/fsdt file extension
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2023-05-10 15:16:16 -07:00 |
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Jerry Zhao
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591c1d6500
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Merge pull request #1464 from ucb-bar/optionals
Make BootAddrReg optional
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2023-05-10 13:03:22 -07:00 |
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Jerry Zhao
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c148f1daf1
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Make BootAddrReg optional
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2023-05-10 11:44:03 -07:00 |
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Jerry Zhao
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7b8cb001ee
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Merge pull request #1465 from ucb-bar/renameserial
Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness
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2023-05-10 11:39:31 -07:00 |
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Jerry Zhao
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fbfb518b72
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Merge remote-tracking branch 'origin/main' into renameserial
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2023-05-10 11:39:11 -07:00 |
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Sagar Karandikar
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1c10f75622
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Merge pull request #1471 from ucb-bar/lowmem-configs
Add 1GB / 4GB DRAM firechip configs for FireSim VCU118
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2023-05-10 11:32:01 -07:00 |
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Sagar Karandikar
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abe8a7fb8b
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remove extra newlines
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2023-05-10 11:31:05 -07:00 |
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Abraham Gonzalez
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f111e2d459
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Merge pull request #1398 from ucb-bar/bump-verilator
Bump Verilator and use `TestDriver.v` as top
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2023-05-10 09:10:34 -07:00 |
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Jerry Zhao
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20250731ea
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Merge pull request #1468 from ucb-bar/dramsim2bump
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2023-05-09 21:33:44 -07:00 |
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abejgonzalez
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d3f148f1f4
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Merge remote-tracking branch 'origin/main' into bump-verilator
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2023-05-09 20:50:07 -07:00 |
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Abraham Gonzalez
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8fa12e38cf
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Merge pull request #1466 from ucb-bar/sync-params-n-script
Separate out conda-lock generation into new script
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2023-05-09 20:41:31 -07:00 |
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Jerry Zhao
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8be6d42606
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Bump DRAMSim2 to avoid verbose log files
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2023-05-09 20:17:17 -07:00 |
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abejgonzalez
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1f687af997
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Generate all lockfiles at once
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2023-05-09 14:12:09 -07:00 |
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abejgonzalez
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dbbf7c90b4
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Separate out conda-lock generation into new script
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2023-05-09 13:58:40 -07:00 |
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abejgonzalez
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e832667cce
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Bump Verilator
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2023-05-09 13:31:00 -07:00 |
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abejgonzalez
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2997cddc0e
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Merge remote-tracking branch 'origin/main' into bump-verilator
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2023-05-09 13:27:13 -07:00 |
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Jerry Zhao
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eced8e63d9
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Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness
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2023-05-08 18:19:18 -07:00 |
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Jerry Zhao
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8b805aca1b
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Merge pull request #1463 from ucb-bar/harness-dir
Move TestHarness to chipyard.harness, make chipyard/harness directory
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2023-05-08 18:17:38 -07:00 |
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Jerry Zhao
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ad98363add
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Update docs/Advanced-Concepts/Harness-Clocks.rst
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
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2023-05-08 18:17:20 -07:00 |
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Sagar Karandikar
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95da9cefb5
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4GB DRAM configs
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2023-05-08 13:41:51 -07:00 |
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Jerry Zhao
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ac281daa78
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Move TestHarness to chipyard.harness, make chipyard/harness directory
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2023-05-08 08:00:56 -07:00 |
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Jerry Zhao
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352cc773b5
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Merge pull request #1445 from ucb-bar/flip_serial_tl
Flip serial_tl_clock to be generated off-chip
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2023-05-08 08:00:23 -07:00 |
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-T.K.-
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3196d44f22
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FIX: fix wording in doc
We don't require the host computer to be x86 (can be RISC-V!)
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2023-05-07 22:22:37 -07:00 |
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Jerry Zhao
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d42b195b91
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Add notes to docs indicating SoftCore bringup with VCU118 is legacy
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2023-05-07 22:22:37 -07:00 |
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Jerry Zhao
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4f5bbdca97
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Flip serial_tl.clock for firechip BridgeBinders
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2023-05-07 22:22:37 -07:00 |
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Jerry Zhao
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9566667767
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Remove bus-to-bus crossings
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2023-05-07 22:22:37 -07:00 |
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Jerry Zhao
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5f076b184d
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Flip serial_tl_clock to be generated off-chip
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2023-05-07 22:22:36 -07:00 |
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