Alon Amid
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6eaac63e1b
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address PR comments
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2020-10-16 06:34:26 +00:00 |
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Alon Amid
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2c935b4ad7
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pull firesim mem model config into firesim tweaks
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2020-10-15 17:07:51 +00:00 |
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Alon Amid
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4a317b0cab
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differentiate default config package delimiter
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2020-10-15 17:07:20 +00:00 |
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Jerry Zhao
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0c46ed1676
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Rename testchip_fesvr to testchip_tsi
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2020-10-09 09:34:20 -07:00 |
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Jerry Zhao
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25129c27ca
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Add testchip_fesvr to uncondtionally used resources
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2020-10-09 09:27:58 -07:00 |
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Jerry Zhao
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d71c3b6357
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Unify htif implementation with firesim
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2020-10-09 09:27:58 -07:00 |
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Jerry Zhao
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3d0022667a
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Bump testchipip
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2020-10-01 22:43:43 -07:00 |
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Jerry Zhao
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b057cfbd8c
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Merge remote-tracking branch 'origin/dev' into clocking-features
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2020-10-01 20:12:20 -07:00 |
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Jerry Zhao
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2db3c90f83
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Merge pull request #648 from ucb-bar/sodor-integrate
Sodor Integration
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2020-10-01 17:31:45 -07:00 |
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Jerry Zhao
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79042e4ce8
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Bump to support firesim simulation of no-AXI4DRAM designs
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2020-10-01 10:21:43 -07:00 |
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Jerry Zhao
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164617e2d6
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Fix no-mbus example design
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2020-10-01 10:20:10 -07:00 |
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Jerry Zhao
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489ae695fc
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Add tile-resetter to all designs
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2020-10-01 10:19:43 -07:00 |
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Zitao Fang
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6c33672c66
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Bump Sodor submodule after merge
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2020-10-01 10:08:39 -07:00 |
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Albert Magyar
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2f5790d611
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Add model multi-threading annotations (ignored by default) to FireChip
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2020-09-30 23:32:49 -07:00 |
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Zitao Fang
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ef03a5efe0
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Bump testchipip
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2020-09-30 14:36:45 -07:00 |
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David Biancolin
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ebfe3103a4
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[clocks] IdealizedPll -> DividerOnlyClockGenerator
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2020-09-29 17:33:49 -07:00 |
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David Biancolin
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5b414f5829
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[clocks] Emit frequency summary for divider-only PLL model
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2020-09-29 16:59:37 -07:00 |
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David Biancolin
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a6ce850391
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[clocks] ClockDividerN: make first output edge occur on first input edge
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2020-09-29 16:19:05 -07:00 |
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Zitao Fang
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f7407709d2
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Attempt to fix CI (2)
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2020-09-25 21:31:12 -07:00 |
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David Biancolin
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b76972d34b
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Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-pll-redux
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2020-09-25 11:02:51 -07:00 |
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David Biancolin
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67145c6ccd
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[clocking] Fix FireSim clock look up
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2020-09-25 10:05:28 -07:00 |
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David Biancolin
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1b3514f95f
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[clocks] Specify a default frequency for TraceGen
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2020-09-25 10:03:46 -07:00 |
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David Biancolin
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7b8a954d04
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[firechip] Rework FireSim clocking to be more similar to default CY targets
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2020-09-24 23:32:07 -07:00 |
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David Biancolin
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cc949aadab
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[clocking] Address some of Colin's PR comments
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2020-09-24 23:28:47 -07:00 |
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David Biancolin
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f6989a1968
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[clocks] Use the periphery frequency as the default
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2020-09-24 23:24:08 -07:00 |
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David Biancolin
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96bf702c3b
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[clocks] Factor out the PLL calculations into their own class
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2020-09-24 23:23:11 -07:00 |
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Zitao Fang
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6641c1f983
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Attempt to fix CI
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2020-09-24 22:42:49 -07:00 |
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David Biancolin
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84195d28bb
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[clocks] Don't override existing take frequency if present.
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2020-09-23 15:29:52 -07:00 |
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Zitao Fang
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a02700a1d4
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Add documentation for sodor
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2020-09-18 23:14:47 -07:00 |
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Zitao Fang
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0c8771c35e
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Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
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2020-09-18 22:33:42 -07:00 |
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Zitao Fang
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a43400acb9
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Update CI
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2020-09-18 15:36:33 -07:00 |
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David Biancolin
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f36183d236
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[clocks] Update AssignerKey name and comment
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2020-09-18 11:28:31 -07:00 |
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Jerry Zhao
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b9622c5132
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Merge remote-tracking branch 'origin/dev' into serial-tl
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2020-09-18 01:00:13 -07:00 |
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David Biancolin
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ad147ec7f2
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[clocks] Remove dealiaser and node injector until they are needed
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2020-09-17 11:43:39 -07:00 |
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David Biancolin
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0f33ea3999
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[clocks] Stringly specified clock frequencies; DRY out schemes
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2020-09-17 11:41:05 -07:00 |
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David Biancolin
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6a26a350ee
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[clocks] Update dealiaser based on feedback
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2020-09-17 11:33:26 -07:00 |
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David Biancolin
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cfa7e30d95
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[clocks] Fix comment in ClockDividerN
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2020-09-17 11:32:51 -07:00 |
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David Biancolin
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b8d3e4a66d
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Update Idealized PLL config
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2020-09-16 16:30:25 -07:00 |
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David Biancolin
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8e4dedcecf
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Remove require guard on divided configs
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2020-09-16 16:30:00 -07:00 |
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David Biancolin
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895bacea98
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WIP - Simple divider-only PLL generation flow
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2020-09-16 16:00:26 -07:00 |
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Jerry Zhao
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269af01a70
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Bump testchipip
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2020-09-16 13:51:33 -07:00 |
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Jerry Zhao
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36ccb12560
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Bump testchipip
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2020-09-16 10:29:03 -07:00 |
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Zitao Fang
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1543acfacd
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Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
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2020-09-14 23:55:05 -07:00 |
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Zitao Fang
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642441e0a2
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Replaced memory and fixed 3-stage single port arbiter
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2020-09-14 23:54:52 -07:00 |
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Jerry Zhao
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0d8e87126c
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Deprecate support for on-chip SerialAdapter
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2020-09-14 19:43:32 -07:00 |
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Jerry Zhao
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f9cc1dc2c2
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Merge remote-tracking branch 'origin/dev' into serial-tl
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2020-09-14 19:35:43 -07:00 |
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Jerry Zhao
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10625a3a6c
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Undo regression in iocells flexibility
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2020-09-14 13:27:31 -07:00 |
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Jerry Zhao
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16c80112a7
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Merge pull request #670 from ucb-bar/harness-refactor
Split IOBinders into IOBinders and HarnessBinders | punch out clocks to harness for simwidgets and bridges
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2020-09-14 12:45:46 -07:00 |
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Zitao Fang
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5506f77679
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Add CircleCI check and update Sodor config
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2020-09-14 09:14:57 -07:00 |
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Jerry Zhao
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6c5bce5430
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Support Tilelink over serial
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2020-09-13 11:59:16 -07:00 |
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