Rename testchip_fesvr to testchip_tsi

2020-10-09 09:34:20 -07:00
parent 25129c27ca
commit 0c46ed1676
3 changed files with 4 additions and 4 deletions
--- a/generators/testchipip
+++ b/generators/testchipip
--- a/generators/utilities/src/main/scala/Simulator.scala
+++ b/generators/utilities/src/main/scala/Simulator.scala
@@ -83,8 +83,8 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
  }
  def resources(sim: Simulator): Seq[String] = Seq(
    "/testchipip/csrc/SimSerial.cc",
-    "/testchipip/csrc/testchip_fesvr.cc",
-    "/testchipip/csrc/testchip_fesvr.h",
+    "/testchipip/csrc/testchip_tsi.cc",
+    "/testchipip/csrc/testchip_tsi.h",
    "/testchipip/csrc/SimDRAM.cc",
    "/testchipip/csrc/mm.h",
    "/testchipip/csrc/mm.cc",