[clocking] Address some of Colin's PR comments

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -28,9 +28,6 @@ import sifive.blocks.devices.spi._
 
 import chipyard._
 
-// Imports for multiclock sketch
-import boom.common.{BoomTile, BoomTileParams}
-import ariane.{ArianeTile, ArianeTileParams}
 // -----------------------
 // Common Config Fragments
 // -----------------------
@@ -167,7 +164,6 @@ class WithDMIDTM extends Config((site, here, up) => {
 
 class WithNoDebug extends Config((site, here, up) => {
   case DebugModuleKey => None
-
 })
 
 class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)

generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala

@@ -55,7 +55,7 @@ case class IdealizedPLLNode(pllName: String)(implicit valName: ValName)
   )
 
 /**
-  * Generates a digttal-divider-only PLL model that verilator can simulate.
+  * Generates a digital-divider-only PLL model that verilator can simulate.
   * Inspects all take-specified frequencies in the output ClockGroup, calculates a
   * fast reference clock (roughly LCM(requested frequencies)) which is passed up the
   * diplomatic graph, and then generates dividers for each unique requested